Vendor: Advanced Architectures Category: FIFO / CAM

Synchronous FIFO with configurable flags and counts

The sFIFO controls are designed to operate over a wide range of clock frequencies.

Overview

The sFIFO controls are designed to operate over a wide range of clock frequencies. The interface signals are fully synchronous; no asynchronous signals are present on either side. Only reset may be asynchronous in that it may be asserted asynchronously and synchronized internally to the clock.

The FIFO also has a programmable fall-through for first data entering an empty FIFO. It may be “0” in which case the input is passed combinatorially to the output, or “1” where the FIFO appears like a simple register.

Key features

  • Fully Synthesizable RTL - Verilog 
  • Static Timing Analysis compatible 
  • Dual-port inferred RAM architecture
  • Configurable width, depth  & fallthrough
  • Standard FIFO handshake interface 
  • Flags or depth values on each port

Block Diagram

A2_sFIFO block diagram

Applications

  • Fully Synchronous buffering in a single clock domain

Specifications

Identity

Part Number
A2_sFIFO
Vendor
Advanced Architectures
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about FIFO / CAM IP core

Frequently asked questions about FIFO / CAM IP cores

What is Synchronous FIFO with configurable flags and counts?

Synchronous FIFO with configurable flags and counts is a FIFO / CAM IP core from Advanced Architectures listed on Semi IP Hub.

How should engineers evaluate this FIFO / CAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this FIFO / CAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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