Video Output Port IP Core

Video Output Port IP Core is a compact and high-performance functional block for embedded system that collects and outputs graphical video data to video display controller.

Video Output Port (VOP) IP Core provides a multi-layer video data output from memory to the display device. The main functions of IP Core are - direct memory access, data buffering, mixing images with alpha channel overlay, generation of clock signals to the display device.

IP core is designed to build systems that require hardware acceleration for graphics output.

• Pixel format: ARGB 32bpp
• Number of layers is a parameter of synthesis
• Layer mixing:
  • With the addition of an alpha channel
  • With a previously added alpha channel
  • With the addition of a constant alpha channel
• Ability to change the size and position of the video window for each layer
• Pan and zoom functionality for images larger than the window
• Support for a hardware cursor.
• Customizable background color.
• Configurable sync signal parameters.

The IP Core is available as either a netlist or VHDL source code. It includes everything required for easy implementation in customer projects.

The delivery package includes:

• Synthesized netlist for the target FPGA device
• Testbench
• Place-and-route script
• Simulation script
• Detailed specification and implementation guide.