High-performance RF front-end module for 5G mobile terminals
The WEA2630FE45G is a high-performance RF front-end module designed for 5G mobile terminals.
- RF Front End
- silicon proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
High-performance RF front-end module for 5G mobile terminals
The WEA2630FE45G is a high-performance RF front-end module designed for 5G mobile terminals.
The Secure Debug IP provides isolation between 2 domains.
WDR (Shadow and Highlight Compensation Core)
ASICFPGA WDR core: All imaging devices need dynamic range correction between source and output display.
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…
Smart card controller core is compliant to ISO 7816 3 specification.
5.72 GHz to 15.04 GHz Low phase Noise Fractional-N Synthesizer
The WEA615S55S is a wide band fractional – N frequency synthesizer with on Chip doubler implemented in ST BiCMOS55 process.
The Ethernet MAC and PCS 10G/25G is a silicon agnostic implementation of the IEEE 802.3 standard.
The Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
In Digital video broadcasting for digital transmission for satellite applications, a FEC (Forward Error Correction) sub-system is…
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
In Digital video broadcasting for terrestrial broadcasting systems, a FEC sub-system is needed.
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…
The BCH decoder has four main functional blocks along with memory blocks.
Networking SerDes IP, Silicon Proven in ST 28FDSOI
The 28 Gbps SerDes PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling…
LVDS Rx IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS Receiver.
Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in IDM 180nm /150nm)
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in ST 28FDSOI
The HDMI receiver PHY (Physical layer), a single-port IP core, complies with all the specifications of HDMI 1.4.
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in ST 28FDSOI
IP core for physical layer HDMI transmitters that fully complies with HDMI 1.4 specifications The HDMI transmitter PHY provides a…
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 130/110G
IP core for physical layer HDMI transmitters that fully complies with HDMI 1.4 specifications The HDMI transmitter PHY supports p…