Vendor: Secure-IC Category: Root Of Trust

Secure Debug Hardware IP

The Secure Debug IP provides isolation between 2 domains.

Overview

The Secure Debug IP provides isolation between 2 domains. It will ensure isolation between the HOST System on one hand, and the HSM System on another hand. Both(HOST an dHSM)can access the IP through an AXI Slave interface.

Secure-IC’s Secure Debug IP is a hardware IP that provides:

  • Hardware Authentication scheme between the HOST and the HSM.
  • Communication interface between the HOST and the HSM,mainly for the purpose of the maintenance of the System-on-Chip.

This IP is controlled by a HOST through an AXI Slave Interface. The purpose of the Secure Debug IP is to provide the following services:

  • Get life-cycle information from the HSM.
  • Provide a Hardware Authentication scheme.
  • Allow only one HOST to be logged in at the same time.
  • Allow to open the HSM debug por tonly if life cycle mode values allow it.
  • Receive Maintenance requests (first programming, update, lifecycle ...) from an external user.

Block Diagram

SCZ_IP_SDEBUG block diagram

Applications

  • Automotive
  • IoT
  • eHealth
  • Defense
  • Payments
  • Servers
  • Smart Grid
  • Identity
  • Media & Entertainment
  • Memory & Storage
  • Consumer Electronics
  • Edge & Cloud
  • Trusted Computing
  • AI
  • Printer
  • Industry

What’s Included?

  • RTL code 
  • SW Drivers 
  • Scripts for  implementation 
  • Self-checking RTL test-bench
  • Documentation

Specifications

Identity

Part Number
SCZ_IP_SDEBUG
Vendor
Secure-IC
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Secure-IC
HQ: France

Learn more about Root Of Trust IP core

Secure-IC Enables World’s First PSA Level 4 Certification within Silicon Labs Series 3’s Secure Vault

This historic milestone validates Secure-IC's cutting-edge technology, namely Securyzr™ S100 series derived from Securyzr™ neo Core Platform, serving as the advanced Root of Trust at the core of the Series 3's Secure Vault. It also demonstrates Silicon Labs' security leadership and stands as a testament to the longstanding partnership between the two companies, where semiconductor innovation meets world -class embedded cybersecurity expertise.

Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems

In a landscape defined by AI acceleration, chiplet-based system integration, and upcoming post-quantum challenges, Secure-IC (booth #1225) will showcase its latest technologies addressing the complex challenges of chiplet security, quantum resilience, automotive-grade protection, and compliance with fast-evolving global security regulations.

Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security

Secure-IC, the rising leader, and global provider of end-to-end cybersecurity solutions for embedded systems and connected objects, has achieved a historical milestone by becoming the first security IP and software vendor worldwide to receive CAVP (Cryptographic Algorithm Validation Program) Hardware certification for its Post-Quantum Cryptography (PQC) algorithms.

Frequently asked questions about Root of Trust IP cores

What is Secure Debug Hardware IP?

Secure Debug Hardware IP is a Root Of Trust IP core from Secure-IC listed on Semi IP Hub.

How should engineers evaluate this Root Of Trust?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Root Of Trust IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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