The ATO00512X1MX180LB52ND is organized as a 512-bit by 1 one-time programmable (OTP).
- eFuse / OTP
- Silicon Proven & Ready for Production
- Now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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The ATO00512X1MX180LB52ND is organized as a 512-bit by 1 one-time programmable (OTP).
128X8 Bits OTP (One-Time Programmable) IP, CanSemi 0.18um 1.8V/3.3V Process
The ATO00128X8CA180L333NA is organized as a 128-bit by 8 one-time programmable (OTP).This is a kind of non-volatile memory fabric…
TCAM can search for data that matches the input in one cycle from all the information stored in the memory.If there are multiple …
BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP.
The Rambus HBM3E / HBM3 controller cores are designed for use in applications requiring high memory bandwidth and low latency inc…
The AES engine IP is a high-performance cryptographic engine operates in AES NIST Federal information processing standard FIPS-19…
The LDPC Error Correction Core (Alcyone) delivers industry- error correction performance to enable 2D/3D, SLC/MLC/TLC/QLC NAND Fl…
The NVMe controller core (Meissa) is compliant with NVM Express 1.4 specification (NVMe 2.0 Mandatory) and targeted for both ente…
Silicon agnostic Ethernet MAC IP for 40G, 100G speeds Ethernet MAC 40G/100G IP is a solution that enables the host to communicate…
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter
The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps.
HDCP Encryption-Decryption Engine
The Trilinear Technologies High-bandwidth Digital Content Protection (HDCP) Encryption Decryption Engine IP core implements the H…
CCSDS turbo encoder with sync marker, pseudo randomiser and input memory
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder with sync marker, optional pseudo-randomiser a…
CCSDS turbo decoder with sync marker synchroniser, descrambler and input memory
This is a CCSDS compatible 16 state error control turbo decoder with optional synchronisation, optional descrambling and input me…
Always-on Voice Activity Detection interfacing with analog microphones.
The WT-a-HD.03 is a mixed analog/digital Virtual Component (ViC) containing a Voice Activity Detection (VAD) engine for ultra-low…
Low-leakage LDO in TSMC 22ULL to supply logic and analog domains (up to 3.63V input supply)
Low-leakage LDO in TSMC 22ULL to supply logic and analog domains (3.3V input supply)
Low-leakage LDO in TSMC 22ULL to supply logic and analog domains (up to 3.63V input supply)
Low-leakage LDO in TSMC 22ULL to supply logic and analog domains (3.3V input supply)
Capless low input voltage LDO in GF 22FDX
Capacitor-less low input voltage LDO regulator in GlobalFoundries 22FDX
Always-on Voice Activity Detection interfacing with analog microphones.
The WT-a-HD.03 is a mixed analog/digital Virtual Component (ViC) containing a Voice Activity Detection (VAD) engine for ultra low…
24-bit Cap-less ADC 101 dB SNR low power and low latency 3 channels
The sADC101-SW3-LR.01 is a mixed (analog and digital) Virtual Component containing two mono ADCs, and additional functions offeri…
24-bit Cap-less ADC 106 dB SNR with ASRC and phase alignement 6 channels
The hexADC-uLP-SW1.01 is a mixed (analog and digital) Virtual Component containing six mono ADCs, and additional functions offeri…