1-56Gbps Serdes - 7nm (Area-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
- Multi-Protocol PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
1-56Gbps Serdes - 7nm (Area-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (PPA-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
The Image Signal Processing (ISP)-- ISI700 receives camera sensor data via the 4-channel DVP interface.
Standard Cell Libraries GF 55nm
The Standard Cell libraries deliver thousands of optimized cells with each one being optimized for power, area, speed, routing, a…
Ceva-NeuPro Studio is a comprehensive software development environment designed to streamline the development and deployment of A…
Advanced graphics and compute acceleration on power constrained devices
Designed for efficiency.
Standard Definition NTSC/PAL/SECAM Video Sync Separator
The DB1800 Video Sync Separator IP Core extracts timing information from a standard NTSC/PAL/SECAM composite sync video signal.
500nm Trimmed Low Power Bandgap
The BG102 is a 1.2V CMOS low power, medium precision CMOS bandgap cell designed for use in a wide variety of mixed signal device …
LPC (Low Pin Count Interface) Verification IP provides an smart way to verify the LPC bi-directional bus.
IPMB Verification IP provides an smart way to verify the IPMB two-wire bus.
GMII TBI (8b/10b) Ethernet Verification IP
The Gigabit Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of desi…
The SD Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Interface of an AS…
The SD Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Interface of an AS…
The I3C Verification IP provides an effective & efficient way to verify the components interfacing with I3C interface of an IP or…
DisplayPort 2.0 Verification IP
The DisplayPort version 2.0 Verification IP provides an effective & efficient way to verify the components interfacing with the D…
The JTAG Verification IP provides an effective & efficient way to verify the components interfacing with the JTAG interface of an…
The Ethernet TSN Verification IP provides an effective & efficient way to verify the components interfacing with an IP or SoC.
Secure RoT Core for Data Centers
Secure RoT with Post-Quantum Cryptography Datacenter-class SoCs such as CPUs, GPUs, DPUs, and NVMe controllers require a trusted …
The Polyphase Video Scaler is a high performance, high quality, video scaler IP core capable of scaling up or down the input vide…