3GPP compliant coding and modulation for Downlink Physical Shared Channels The Physical Downlink Shared Channel (PDSCH) is used f…
- Channel Coding
- Now
- 3GPP 5G NR
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
3GPP compliant coding and modulation for Downlink Physical Shared Channels The Physical Downlink Shared Channel (PDSCH) is used f…
1024-bit EEPROM IP with configuration 32p2w16bit
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1024 bits (16(bit per word) x…
The agileVGLITCH voltage monitor provides security and protection against voltage side-channel attacks (SCA) and tampering such a…
Temperature Sensor (Analog Output)
The agileTSENSE_A GP Temperature Sensor is a traditional ΔVBE temperature sensor that amplifies the difference between two VBE vo…
General Purpose BandGap Reference
The agileREF consists of a bandgap reference core together with a bandgap reference voltage generator (VREF), VREF replica curren…
The agileRCOSC is based on a traditional architecture which allows for the frequency to be trimmed to remove the effects of proce…
The agilePOR GP is a Power-On-Reset circuit.
The agileLDO_LP is a linear regulator, suitable for use in any low power, low current system and is designed to provide a flexibl…
The agileIRDROP I-R Drop Sensor is a circuit to detect supply I-R drops within the system.
The agileDSCL is a compact Digital Standard Cell Library customizable for specific foundries and processes, and optimized for low…
Programmable-Threshold Comparator
The agileCMP GP Programmable Threshold Comparator features a user-selectable (enable/disable) hysteresis as well as programmable …
The agileCAM is a Ring Oscillator (RO) based clock attack monitor designed to detect clock attacks due to violation of the set-up…
CCSDS 131.2 Wideband Demodulator
The Creonic CCSDS high performance wideband demodulator performs all tasks of an inner receiver.
2MHz 1.71-5.5V Oscillator - Low Power, ± 1% accuracy at @ 27oC after trimming
The CM4043hh is a low power, high-accuracy, output glitch-free, wide supply voltage range, general purpose 2MHz oscillator.
10-bit 1-channel 10 to 150 MSPS SAR ADC
055TSMC_ADC_13 is a 10-bit 1-channel SAR ADC with sample rate from 10 to 150 MSPS that operates with 1V peak-to-peak input signal.
ComputeRAM is an SRAM macro with integrated compute capability.
Bandwidth and area optimized low power memory interface solution tuned for AI, HPC, data centers and networking conforming to HBM…
Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications
ISO/IEC 21122-1 JPEG-XS Standard Codec
Jointwave X16 is a JPEG XS Codec (Encoder + Decoder) designed for visually lossless, real time video transmission/storage.
10Gbps Multi-Link and Multi-Protocol PHY IP
Designed for multi-protocols running on single PHY macro and is compliant with USB 3.1, PCI Express (PCIe) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, QSGMII