HBM3 PHY & Controller

Bandwidth and area optimized low power memory interface solution tuned for AI, HPC, data centers and networking conforming to HBM3 (JESD238A) JEDEC standards

• One stop PHY & Controller solution with an average random efficiency of more than 85%
• Supports up to 6400 MT/s for HBM3 and up to 9600 MT/s for HBM3E
• DFI 5.1 compatible interface to the memory controller
• Flexible PHY with programmable intelligent interface training sequences
• Flexible IEEE1500 interface to support memory vendor customizations
• Supports up to 32Gb density per die
• Supports up to 16H HBM3 DRAM stacks
• Supports major 2.5D/3D packaging technologies including support for interposer designs and interconnect and memory repairs
• Add-on features/engines for MPFE, RAS and Debug available upon request
• Add-on feature for generic 2.5D die-to-die data transport interconnect

• Data center and networking
• High performance computing (HPC)
• Artificial intelligence (AI)
• High-end graphics

• Executable .run installation file
• GDSII, LEF Files, LVS netlists, .lib/.db
• timing models, Verilog model, DRC/LVS log files, I/O IBIS model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files
• sample verification environment, PHY data book
• physical implementation guide, application notes, verification guide, installation guide, implementation checklist
• The PHY Utility Block includes Verilog code, synthesis/STA constraints and scripts, sample verification environment, data book