Key considerations and challenges when choosing LDOs
The vast array of on-chip LDO options and characteristics can make the selection process complex.
Vendor:
Agile Analog
Category:
LDO Voltage Regulator
Low Power Regulator
The agileLDO_LP is a linear regulator, suitable for use in any low power, low current system and is designed to provide a flexibl…
Overview
The agileLDO_LP is a linear regulator, suitable for use in any low power, low current system and is designed to provide a flexible range of regulated output voltages suitable for ultra-low power systems and near-vt operating modes.
The agileLDO_LP consists of: A voltage reference generator, an error amplifier and a output current source. The regulated output voltage is fed-back into the error amplifier to maintain a constant regulated output over the specified range of input voltages and load currents.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.
Key features
- Input voltage range: 1.62 to 1.98V
- Regulated output voltage: 0.825V (typical)
- Active current: 2.5mA (typical) • Powered-down current: 15nA (typical)
- Silicon area: 0.024 mm2 in 16nm technology
- PSRR: @DC: 80dB (typical), @ILOAD = 0.9*ILOAD|MAX), @f = 1MHz: 10dB (typical), @ILOAD = 0.9*ILOAD|MAX)
Block Diagram
agileLDO_LP block diagram
Benefits
- High Performance
- - Low Noise and High PSSR for noise-sensitive analog circuits
- Sense Input
- - Low Noise and High PSSR for noise-sensitive analog circuits
Applications
- IoT, Security, Automotive, AI, SoCs, ASICs
What’s Included?
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report
Specifications
Identity
Part Number
agileLDO_LP
Vendor
Agile Analog
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
United Kingdom
Learn more about LDO Voltage Regulator IP core
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The Tradeoffs of Low Dropout (LDO) Voltage Regulator Architectures and the Advantages of "Capless" LDOs
Power management of battery-powered electronic devices is becoming increasingly more important for the microelectronics industry. This white paper details the difference between low dropout (LDO) voltage regulators that use external output capacitors and those that do not, and how your system designs can benefit from not using an output capacitor. Well-designed capless LDO voltage regulators can have multiple benefits, and they are presented here.
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Power management poses challenges
Power management poses challenges
Tradeoffs of LDO Architectures and the Advantages of Advanced Architecture "Capless" LDOs
Power management of battery-powered electronic devices is becoming increasingly more important for the present and future microelectronics industry. This application note details the difference between low dropout (LDO) voltage regulators that use output capacitance and those that do not and how your system designs can benefit from or be improved by not using an output capacitor.
Frequently asked questions about LDO Voltage Regulator IP cores
What is Low Power Regulator?
Low Power Regulator is a LDO Voltage Regulator IP core from Agile Analog listed on Semi IP Hub.
How should engineers evaluate this LDO Voltage Regulator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LDO Voltage Regulator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.