Introducing agileSecure anti-tamper security portfolio
Agile Analog’s tamper detection IP is a comprehensive set of sensors and monitors designed to detect a wide variety of physical attacks and side-channel attacks (SCAs). T
Vendor:
Agile Analog
Category:
Power On Reset (POR)
Power-On-Reset Circuit
The agilePOR GP is a Power-On-Reset circuit.
Overview
The agilePOR GP is a Power-On-Reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis to avoid false resets in noisy environments.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.
Key features
- Start-up Time: max 10us
- Configurable Threshold
- Programmable Delay
- Uses Hysteresis to avoid false resets in noisy environments
- Current Consumption1: typ 100nA
- Customizable design for simple SoC integration
Block Diagram
agilePOR block diagram
Benefits
- Hysteresis
- - Avoids false resets due to noisy environments
- Configurable thresholds
- - Both upper and lower thresholds are programmable
- - Microprocessor held in reset during voltage rail ramp-up and during brown-out conditions
Applications
- Combine with agileVGlitch and agileLDO to create a self contained voltage attack sensor sub-system.
What’s Included?
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report
Specifications
Identity
Part Number
agilePOR
Vendor
Agile Analog
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
United Kingdom
Learn more about Power On Reset (POR) IP core
Method for Booting ARM Based Multi-Core SoCs
In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software.
Analysis of RDC Paths for a million gate SoC
Reset is necessary to initialize the system and reach to a known state. Just like multiple clocks are required in an SoC to sustain various use models and performance, multiple resets are designed to cater different functional requirements. With this advent we also invite some issues due to crossings among different reset domains. In a sequential design, if the reset of source register is different from the reset of destination register even though the data path is in same clock domain, this will become asynchronous crossing path and can cause metastability at destination register.
The silicon enigma: Bridging the gap between simulation and silicon
VLSI design teams are eagerly anticipating the full functional fab out Silicon to portray their months of hard work, on the other hand the Test teams are busy planning their functional coverage (to fill in the gaps of scan (atpg) patterns coverage holes) but more often than not, the unexpected happens and the teams are busy debugging the Si bring up for functional cases. This paper is trying to highlight the seemingly innocuous issues that occur on first few day of Si bring up and proactive steps that would help reduce these cycle.
BIST Verification at SoC level
With the increase complexity of modern day SoCs, the number of memory blocks and LBIST partitions are increasing, which is in turn making the verification efforts quite challenging. This paper highlights the key points to keep in mind while deciding the verification strategy for self-test, and what are the road-blocks in executing this “ideal” verification plan.
High Density - Low power Flip-Flop
In a current trend of SoC Design, IC’s are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult.
Frequently asked questions about Power-On Reset (POR) IP cores
What is Power-On-Reset Circuit?
Power-On-Reset Circuit is a Power On Reset (POR) IP core from Agile Analog listed on Semi IP Hub.
How should engineers evaluate this Power On Reset (POR)?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power On Reset (POR) IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.