Vendor: Agile Analog Category: Power On Reset (POR)

Power-On-Reset Circuit

The agilePOR GP is a Power-On-Reset circuit.

Overview

The agilePOR GP is a Power-On-Reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis to avoid false resets in noisy environments.
‍
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.

Key features

  • Start-up Time: max 10us
  • Configurable Threshold
  • Programmable Delay
  • Uses Hysteresis to avoid false resets in noisy environments
  • Current Consumption1: typ 100nA
  • Customizable design for simple SoC integration

Block Diagram

agilePOR block diagram

Benefits

  • Hysteresis
  • - Avoids false resets due to noisy environments
  • Configurable thresholds
  • - Both upper and lower thresholds are programmable
  • - Microprocessor held in reset during voltage rail ramp-up and during brown-out conditions

Applications

  • Combine with agileVGlitch and agileLDO to create a self contained voltage attack sensor sub-system.

What’s Included?

  • Datasheet
  • Testing and Integration Guide
  • Verilog Models
  • Floorplan (LEF)
  • Timing models (LIB)
  • Netlist (CDL)
  • Layout (GDS)
  • Physical Verification Report
  • Design Report

Specifications

Identity

Part Number
agilePOR
Vendor
Agile Analog
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Agile Analog
HQ: United Kingdom

Learn more about Power On Reset (POR) IP core

Overcoming power management IP challenges

With modern chips, power management sits right at the core of the architecture. Between scaling down to advanced nodes and pushing for maximum performance-per-watt, managing power has become one of the most complex, high-risk parts of silicon design. Here is what engineering teams are actually dealing with.

Understanding security certification and how analog IP can help

This Agile Analog blog post outlines the security certification process and the impact of implementing analog anti-tamper solutions. With new security measures such as the EU’s Cyber Resilience Act (CRA) regulations becoming fully enforced in 2027, there is increasing interest in security certification and the analog IP that companies can use to detect and prevent security attacks.

Providing protection against EMFI attacks

This Agile Analog blog post is focused on describing the dangers of Electromagnetic Fault Injection (EMFI) attacks and outlining the importance of EMFI sensors that are designed to provide protection.

Frequently asked questions about Power-On Reset (POR) IP cores

What is Power-On-Reset Circuit?

Power-On-Reset Circuit is a Power On Reset (POR) IP core from Agile Analog listed on Semi IP Hub.

How should engineers evaluate this Power On Reset (POR)?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power On Reset (POR) IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP