A efficient pipelined radix-2 squared FFT.
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
A efficient pipelined radix-2 squared FFT.
LVDS-based IOs The Bi-directional LVDS is in production from 90nm CMOS to 16/12nm FinFET and taped out in 7nm FinFET.
5 to 20 MHz Intermediate-frequency amplifier
IFA consists of 3-stages amplifier with tunable gain, AGC system, linear output buffer for differential analog output, analog-dig…
9-bit 2-channel 0.5 to 33 MSPS (8 to 500 kHz BW) delta-sigma ADC
The block is second order delta-sigma ADC with 5-level quantizer.
The AES MPEG-TS interface core allows to encrypt or decrypt MPEG-TS stream using the MVD AES encryption core.
8 to 512 kHz intermediate-frequency amplifier
The device is a t2-channel intermediate-frequency amplifier (IFA).
Stallable pipeline stage with width contraction
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with width expansion
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with protocol for multiway pipeline fork and join capability
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
LDO voltage regulator (output voltage 0 to 1.8 V)
Power supply voltage stabilizer converts supply voltage to voltage of the specified value and operates in two modes: DC/DC step d…
Programmable LDO voltage regulator (output voltage 1.6 to 2.2 V)
The regulator stabilizes the external voltage (supply voltage) and forms an output level of the specified value.
1.17 V Reference current and voltage source
Reference current and voltage source is used to supply any analog blocks.
RSA/ECC Public Key Accelerators with TRNG and AHB
The PKA-IP-150 is a family of Public Key Accelerators (PKA) IP cores designed for full scalability and an optimal “performance ov…
The AES-IP-38 (EIP-38) is IP for accelerating the AES symmetric cipher algorithm supporting GCM or XTS modes at extreme speeds up…
Small is beautiful...
NIST ESV certified, AIS-31, FIPS (SP800-90A/B/C) True Random Number Generator
The TRNG-IP-76 is a FIPS-compliant and certified IP core for True Random Number Generation (TRNG) with an optional post-processor…
RSA/ECC Public Key Accelerator Farm with TRNG and AHB
The EIP-154 PKI Farm engine, offers autonoumus processing of Public Key Operations.
Highly effective and small gate size Mosquito Noise Reducer
JVC KENWOOD's Mosquito Noise Reducer IP, which is already used in its products, is now available for licensing.
JPEG Codec 4K(YUV422) 96fps@200MHz,
The KJN-7EX conform to the JPEG baseline format/JPEG Extended DCT-based process for compressing/decompressing 8bit/12bit still im…
Display Controller – 4K Digital Cinema LCD Panels (AXI4/AXI Bus)
The DB9000AXI-DCI LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Inte…