eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
RapidFlex eFPGA IP provides a reconfigurable, upgradeable, and iterative logic computing layer for SoCs, MCUs, AI accelerators, i…
Our Standard Cell Libraries are designed to meet the rigorous demands of modern semiconductor applications, including automotive,…
The GDDR7 controller IP core is designed for use in applications requiring high memory throughput including artificial intelligen…
Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces
Expands effective bandwidth across links and memory interfaces with deterministic, data-independent latency, fully pipelined to sustain line rate
SmartDV’s UCIe 3.x Controller IP is a next-generation Universal Chiplet Interconnect Express solution engineered for the most dem…
Rambus offers the industry’s fastest HBM4E Controller IP core designed to support customers with deploying a new generation of HB…
The 56G/64G PAM4 SERDES hard macro IP delivers a high-performance, low-power solution for high-speed serial interfaces.
The UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets, fully compliant with the Universal …
The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
The PCI Express® (PCIe®) Controller IP is a configurable, performance-optimized core designed for ASIC and FPGA integration.
GDDR5 Controller - Verifies memory compliance, boosts performance, and ensures reliability
The GDDR5 Memory Controller Verification IP (VIP) is a robust solution designed to verify the compliance and performance of GDDR5…
Rambus is offering the industry’s first HBM4 Controller IP core designed to support customers with deploying a new generation of …
UCIe Die-to-Die Chiplet Controller
The UCIe Controller IP is a configurable and customizable UCIe 1.1 compliant die-to-die controller.
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…
Traditional processors no longer strike the right balance between high performance, energy consumption, and cost.
Ultra High-Performance AES-GCM/CTR IP
The proliferation and expansion of connected devices, connectivity infrastructure, cloud computing, and artificial intelligence i…
Neoverse Compute Subsystems N3 (CSS N3)
The Performance-per-Watt Arm Neoverse N3 Platform Validated by Arm for Networking and Edge Markets configurable to target 5G, DPU…
Compute Express Link (CXL) FPGA IP
Industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.
Single 1024-bit SIMD DSP for Vision/Radar/Lidar/AI
AI DSA Processor - 9-Stage Pipeline, Dual-issue
NI900 is a DSA processor based on 900 Series.