1G to 50G Single-Port MACsec Engine with xMII interface and TSN support
The MACsec-IP-361 is a plug-and-play solution for adding MACsec on the xMII side of an Ethernet subsystem.
- MACsec
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
1G to 50G Single-Port MACsec Engine with xMII interface and TSN support
The MACsec-IP-361 is a plug-and-play solution for adding MACsec on the xMII side of an Ethernet subsystem.
The ICE-IP-63 (EIP-63) is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well …
High-speed Inline Cipher Engine
The ICE-IP-338 (EIP-338) Inline Cipher Engine is a scalable, high-performance, multi-stream inline cryptographic engine that offe…
Inline cipher engine with AXI, for memory encryption
Modern computing architectures must address increasing concerns regarding off-chip data confidentiality.
Inline memory encryption engine, for FPGA
IME-IP-340 Inline Memory Encryption (IME) Engine provides just-in-time encryption, decryption and authentication for all memory r…
Programmable Root of Trust With DPA and FIA for US Defense
The Rambus Root of Trust RT-1660 is a fully programmable, FIPS 140-3 compliant root-of-security core offering security by design …
PCIe Controller for USB4 with AXI
The PCIe Controller for USB4 (formerly XpressRICH) is a configurable and scalable PCIe controller IP designed for ASIC and FPGA i…
The PCIe Controller for USB4 (formerly XpressRICH) is a configurable and scalable PCIe controller IP designed for ASIC and FPGA i…
The ARINC 429 IP is a high-performance solution for integrating ARINC 429 data buses into avionics systems.
JPEG XS compression IP core for HD - Max fps: 1920 - Color sampling: 4:2:2 / 4:0:0
intoPIX has developed various optimized TicoXS architectures running a different pixel per clock to target a wide range of resolu…
JPEG XS Codec with Flawless Imaging - Max res: 4096x2160 - Max fps: 30 (4:4:4), 60 (4:2:2/ 4:2:0)
TicoXS FIP combines JPEG XS with an Flawless Imaging Profile (FIP) to deliver more compression efficiency on any content guara…
This SATA 3 Controller IP enables fast and efficient connectivity for storage devices, supporting high-speed data transfer.
Highly customizable processor IP supporting the Lua scripting language
A customizable processor IP, that supports the Lua scripting language.
The core idea behind the Universal PHY is to enable open chiplets for a broad range of applications.
The Ceva-Waves Links200 is a fully integrated multi-protocol wireless platform in TSMC 12nm FFC+ supporting Bluetooth High Data T…
The Die-to-Die interface is a functional block that provides a data interface between two chip dies within the same package.
MSquare's eDP PHY is a reliable solution for display interface requirements, supporting resolutions of 4K and higher.
MSquare's ONFI 5.1 PHY is a high-performance and low-power PHY IP, which supports all modes of the Open NAND Flash Interface (ONF…
MSquare's LPDDR5X/4X PHY is a transceiver physical layer IP interface solution designed for ASICs and SOCs.
MSquare's LPDDR4X PHY is a transceiver physical layer IP interface solution designed for ASICs and SOCs.