JPEG Codec 4K(YUV422) 48fps@200MHz. (4Sample/clk)
The KJN-6 conform to the JPEG baseline format for compressing/decompressing still images.
- Video Processing
- We also accept customization according to customer needs.
- ISO/IEC 10918-1, ITU-T T.81
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
JPEG Codec 4K(YUV422) 48fps@200MHz. (4Sample/clk)
The KJN-6 conform to the JPEG baseline format for compressing/decompressing still images.
JPEG Encoder Full HD(YUV422) 48fps@100MHz. (2Sample/clk)
The KJN-4ENC conform to the JPEG baseline format for compressing still images.
JPEG Codec Full HD(YUV422) 48fps@100MHz. (2Sample/clk)
The KJN-4 conform to the JPEG baseline format for compressing/decompressing still images.
JPEG Encoder Full HD(YUV422) 24fps@100MHz. (1Sample/clk)
The KJN-1ENC conform to the JPEG baseline format for compressing still images.
JPEG Codec Full HD(YUV422) 24fps@100MHz.(1sample/clk)
The KJN-1+ conform to the JPEG baseline format for compressing/decompressing still images.
The LCD01G is a fully compatible GEO Mobile Radio (GMR-1) LDPC error control decoder.
Multi Function Viterbi Decoder
The VA08VA is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
Ultra-low-power 2.4 GHz transceiver for Bluetooth 5.3, 802.15.4 and IoT
icyTRX for the most demanding low-power applications The icyTRX ultra-low-power RF transceiver is designed to meet standards such…
100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 80…
Rail to rail LVDS receiver 1 Gbps
LVDS_RX is LVDS receiver with rail to rail input range.
The interface to the core logic includes signal pin (INP) to transmit data and control pin ( EN) to configure the state of the tr…
ISO/EIC 7816 and EMV4.3 UART, with protocol controller and timers
The ISO7816 UART contains all of the digital logic necessary to communicate with an ISO/IEC 7816 or EMV 4.3 integrated circuit ca…
12-bit 2-channel 5 to 7.5 MSPS cascade delta-sigma ADC
The block is third order cascade (2-1) delta-sigma ADC with 5-level quantizer in both stages.
Four-Wire slave IP for use with the Mentor M8051W and M8051EW
The M4WIS adds four-wire slave capability to the M8051W and M8051EW microcontroller designs that are compatible with the I2C Fast…
Two-Wire slave IP for use with the Mentor M8051W and M8051EW
The M2WIS adds two-wire slave capability to M8051W and M8051EW designs.
Noesis Technologies ntOFDM_BBP is a custom baseband processor, which implements the physical layer of an OFDM, time division dupl…
8-Channel PCM-to-PWM Modulator in Fujitsu 55nm
The AR35F01A is a digitally coded conversion IP that translates 8-ch (4 stereo channels) of 16-24bit pulse-code modulated (PCM) i…
The PowerVR Series7XT family pushes mobile and embedded GPU performance to new heights with configurations featuring 2 to 16 clus…
3.3V to 1.2V voltage regulator - UMC 55nm
The cell is a low power series 3.3V to 1.2V voltage regulator.
IP