12-bit 2-channel 5 to 7.5 MSPS cascade delta-sigma ADC

The block is third order cascade (2-1) delta-sigma ADC with 5-level quantizer in both stages. The block consists of:
- Two delta-sigma modulators second and first order, coupled in series and combined by noise cancellation logic
- Clock splitter
- Block of bias currents, tunable (3-bit control)
- Block of reference voltages, tunable (5-bit control)
- Clock frequency divider (4-bit control)
- DWA-correction of capacitors’ mismatch
Output signal is represented in thermometer code at the output of each stage. There is a possibility to disable the second stage of modulator to save the power with decreased accuracy. Next to options included: DWA correction algorithm; tuning of reference voltages buffers; tuning of bias current for operational amplifiers with 3-bit control; the clock frequency divider with integer ratio 1- 15.
Input signal common mode voltage is 1.65 V; recommended values of reference voltages: 0.9 ± 0.4 V; recommended differential input signal amplitude - 0.64 V; allowable duty cycle: 50 ± 5%.
 

• iHP SiGe BiCMOS 0.13 um
• Resolution 8/10 bit
• Operational amplifiers’ current adjustment
• Supply voltage - 3.3 V
• Input differential signal range - 2 V
• Clock frequency divider
• Portable to other technologies (upon request)

• Analog to digital conversion of wide-band signal
• Receivers, transceivers
• Analog integral circuits
• Measurement environment
• Medicine environment

• Schematic or NetList
• Abstract model (.lef and .lib files)
• Layout view (optional)
• Behavioral model (Verilog)
• Extracted view (optional)
• GDSII
• DRC, LVS, antenna report
• Test bench with saved configurations (optional)
• Documentation