DVB-T/H Modulator - RF output with AD9789 DAC
The MVD DVB-T/H modulator is a drop-in module for FPGA that includes the following functions : • Input data framer from Microproc…
- DAC
- Available
- EN 300 744 V1.5.1
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
DVB-T/H Modulator - RF output with AD9789 DAC
The MVD DVB-T/H modulator is a drop-in module for FPGA that includes the following functions : • Input data framer from Microproc…
Super-Fast, Configurable 16-bit 80251 Microcontroller Core
The S80251XC3 core implements a high-performance 16-bit microcontroller that executes the MCS®251 & MCS®51 instruction sets and i…
Hyperbus Flash Memory Controller
Emerging high-performance applications demand increasingly fast read throughputs from NOR-flash memory devices.
High-availability Seamless Redundancy and Parallel Redundancy Protocol (HSR and PRP, IEC 62439-3 Clause 5 and 4 respectively) Edition 4.0 protocols
DPA Resistant Software Library
Addressing the growing demand for readily available solutions that implement Differential Power Analysis (DPA) countermeasures, w…
Emulation of RF and channel impairments in Verilog
The BAY9 Virtual RF (VRF) is an IP core written in Verilog, that allows to emulate most system aspects of a typical RF transmissi…
Silicon-proven, High Density and Low Power Static Random Access Memories
Spectral MemoryIP™ is set of silicon-proven, High Density and Low Power Static Random Access Memories.
Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output
This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 …
LNA is consists of two bipolar amplifier stages.
2-bit 1-channel 50 MHz flash ADC
The circuit is 2-bit ADC with programmable threshold.
Small, ultra-low-power, and very processing-efficient 32-bit processor
The Beyond BA20 PipelineZero Embedded Processor implements a small, ultra-low-power, and very processing-efficient 32-bit process…
SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
The DB-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (bot…
2.5 Gb/s Digital RF Up Converter for AD9739A
The MVD Upconverter core is a drop-in module that converts multiple baseband I-Q signals to analog RF signal with AD9739 or AD973…
The DZ80 is an , 8-bit microprocessor, with 208 bits of user-accessible registers.
High Speed UART IP core - Universal Aysynchronous Receiver / Transmitter
The D2698 is a Octal UART Core software compatible with the SC2698.
Configurable UART with FIFO, software and hardware flow control
The D16950 is a soft core of a Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the OX16C950.
The SPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and…
Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
The SPI IP is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory.
LIN 2.2, 2.1 and 1.3 Protocol Controller IP
The LIN is a soft core of the Local Interconnect Network (LIN).
Used for controlling HDLC/SDLC transmission protocols
The DHDLC IP Core provides versatile support for a widely used HDLC transmission protocol.