Vendor: MVD Cores Category: DAC

DVB-T/H Modulator - RF output with AD9789 DAC

The MVD DVB-T/H modulator is a drop-in module for FPGA that includes the following functions : • Input data framer from Microproc…

Overview

The MVD DVB-T/H modulator is a drop-in module for FPGA that includes the following functions :
• Input data framer from Microprocessor, DVB-SPI source (MPEG-TS flow)
• DVB-T modulator◦Energy dispersal
◦ Reed Solomon encoder
◦ Convolutional interleaver
◦ FEC convolution encoder
◦ Inner interleaver
◦ QPSK/QAM symbol mapper
◦ Framer with pilots & TPS inserter
◦ IFFT and guard interval insertion
• Low pass filter
• Output for complex DAC (2 x 16 bits)

Key features

  • ETSI, DVB-T/H (EN 300 744 V1.5.1) compliant baseband transmitter for Digital Terrestrial Television
  • • Supported FPGA families: Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq
  • • Single clock
  • • Robust SPI input (discarding of incorrect input packets)
  • • PCR re-stamping
  • • Single channel, supports hierarchical transmission
  • • Configurable Convolutional Rate
  • • Configurable in-depth interleaving for DVB-H
  • • Programmable QPSK, 16-QAM and 64-QAM Symbol Mapping
  • • Configurable support for 2k, 8k and 4k (DVB-H) OFDM modes
  • • Programmable Guard Interval (1/4, 1/8, 1/16, 1/32)
  • • Supports variable channel width 5 to 8 MHz
  • • Base band output for complex DAC (2 x 16 bits)
  • • Full synthesizable RTL VHDL design (not delivered) for easy customization
  • • Design delivered as Netlist
  • • MER > 40 dB
  • • Carrier suppression > 45 dB

Block Diagram

Applications

  • The MVD DVB-T/H modulator may be used in applications related to terrestrial transmission, typically at the head end.

What’s Included?

  • #NAME?

Specifications

Identity

Part Number
MVD_DVB_TH_AD9789
Vendor
MVD Cores
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: France

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is DVB-T/H Modulator - RF output with AD9789 DAC?

DVB-T/H Modulator - RF output with AD9789 DAC is a DAC IP core from MVD Cores listed on Semi IP Hub.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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