Overview
Spectral MemoryIP™ is set of silicon-proven, High Density and Low Power Static Random Access Memories. The library consists of the standard 5 compiler architectures: Single Port & Dual Port SRAMs, ROM, One and Two Port Register Files.
Spectral's solutions use foundry or Spectral custom designed bit cells that enable robust operation. They integrate high density, low power architectural design as well as performance optimized circuitry to attain high speed operation with minimal power consumption. Coupled with Spectral's Memory Development Platform, MemoryIP™ is also available in source code format so that users can modify the designs, port to other technologies or extend the capabilities. Spectral MemoryIP™ is designed for standard CMOS process technology.
Learn more about SRAM IP core
The authors propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO2/ZrO2/HfO2 (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology.
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vincent van der Leest, Synopsys
Increasing popularity of AI applications and DPU architecture has led to growing demand for higher SRAM densities, in turn placing challenges on SRAM yield and reliability.
This article explores the relative performance of SRAM PUF and quantum-derived semiconductor PUF technologies for IoT security.
