64-bit High performance Quad Core RISC-V Microprocessor
VEGA AS4161 features a quad core out-of-order processing engine with a 16-stage pipeline for high performance compute requirement…
- RISC-V
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
64-bit High performance Quad Core RISC-V Microprocessor
VEGA AS4161 features a quad core out-of-order processing engine with a 16-stage pipeline for high performance compute requirement…
64-bit High performance Dual Core Microprocessor
VEGA AS2161 features a dual core out-of-order processing engine with a 16-stage pipeline for high performance compute requirement…
64-bit High performance Single Core Microprocessor
VEGA AS1161 features an out-of-order processing engine with a 16 stage pipeline enabling it to meet next gen computational requir…
64-bit RISC-V Single Core Microprocessor
VEGA AS1061 features an in-order processing engine with a 6 stage pipeline enabling it to meet high-performance embedded applicat…
32-bit RISC-V High Performance Microcontroller Class Processor
VEGA ET1031 is a compact 3-stage in-order 32-bit RISC-V processor core ideal for low power applications.
The NFC IP is a NAND Flash Controller for accessing user data from NAND Flash chips. It provides standard AXI interface for the ease of integration in SoC design.
TTEEnd System A664 Core IP is a RTCA DO-254 DAL A certifiable solution which can be used in integrated modular avionics systems.
IP platform for intelligence gathering chips at the Edge
Designed to be the solution for an AI compute device right at the Edge, Sondrel’s new SFA 100 IP reference platform makes creatin…
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+
The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification with support…
The SiFive Performance™ P500 application processor features a thirteen-stage, triple-issue, out-of-order pipeline compatible with…
DVB-S2/S/T2/T/C Combo Demodulator IP (Silicon Proven)
The is a single-chip DVB-T, T2, C, S and S2 demodulator IP core extratced from production chip and silicon proven IP core.
GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 40LP
An IEEE 802.3u compliant single-port Ethernet physical layer transceiver with low power consumption for 10BASE-Te and 100BASE-TX …
SM4 (former name “SMS4”) is a cryptographic standard published by the Office of State Commercial Cryptography Administration (OSC…
SM3 is a hash algorithm initially published by the Office of State Commercial Cryptography Administration (OSCCA) of SCA in 2010,…
CYB-AES implements Rijndael cipher encoding and decoding in compliance with the NIST Encryption Standard.
DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
The LPDDR4/ DDR4/ DDR3L Combo PHY IP offers low latency and supports throughput of up to 1866Mbps.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
Data rates for the DisplayPort transmitter PHY version 1.4 range from 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)