Cryptographic engine using the DES, Triple-DES or AES
The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES, AES or SM4 algorithms.
AHB DES and Triple DES with DMA
The AHB DES/TDES Encryption/Decryption Engine is a configurable core that interfaces to an AHB microprocessor bus.
This core is a full implementation of the Triple DES encryption algorithm.
DES Encryption and Decryption Processor
The IP-ALDES core is the VHDL model of the processor, that performs DES encryption and decryption.
The eSi-DES block performs encryption and decryption of 64-bit words using the DES (Data Encryption Standard) and TDEA (Triple DE…
Ultra-Compact Data Encryption Standard (DES/3DES) Core
The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data…
The DES/3DES crypto engine offers a hardware implementation of the Data Encryption Standard (DES) according to Federal Informatio…
Multipurpose Security Protocol Accelerator
The Multipurpose Security Protocol Accelerator (SPAcc) offers designers unprecedented configurability to address the complex secu…
Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environ…
VeriSyno provides a flexible and configurable security IP solution, which includes common symmetric encryption algorithms, random…
Multipurpose Security Protocol Accelerator - Functional Safety ASIL B support
The Multipurpose Security Protocol Accelerator (SPAcc) offers designers unprecedented configurability to address the complex secu…
MIPHY Consumer SerDes IP, Silicon Proven in ST 28FDSOI
Consumer Multimedia Applications: Wide support of Consumer PHY standards such as PCIe Gen1/2/3, USB 3.0 Super Speed, JESD204B, SA…
Primeexpress PCIE Gen5 digital controller from Primesoc, is well architect,high performance, modular designed and tailor made to …
The 3DES core is a drop-in module that includes the following functions : • 192-bit key size • Single or Triple Data Encryption S…
NT1046 is a single-chip RFID reader solution.
The Encryption Standard (AES) IP Core is a hardware implementation encryption/decryption algorithm described in the U.S.
The 3DES-IP-16 (EIP-16) is IP for accelerating the AES symmetric cipher algorithm (FIPS-46/81 – SP800-IP-20), supporting single D…
The MW_AES core performs the digital baseband function that can be used to protect electronic data.
Floating Point FFT/IFFT IP Core
The Floating Point FFT IP Core (FpFft) is the most versatile available in the industry.
This core family implements various aspects of the AES ( Encryption Standard) algorithm.