Overview
The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard. It processes 64-bit blocks, with one, two, or three 56-bit keys.
Basic core is very small (3,000 ASIC gates). Enhanced versions are available that support
various cipher modes (ECB, CBC, OFB, CFB,
CTR).
The design is fully synchronous and available in both source and netlist form. Test bench
includes the NIST DES test vectors.
DES Core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.
Learn more about Symmetric Crypto IP core
IP Cores, Inc. announces the release of the new LZR4D single-engine ultralow-latency lossless decompression core for the LZ4 format, delivering 256 bits of decompressed data per clock with less than 30 clock cycles of latency.
IP Cores, Inc. announces shipments of the FFT4T core for RF signal processing systems
IP Cores, Inc. announces shipments of the newly released PQC1 Post-Quantum Cryptography Accelerator Core that supports both ML-KEM (FIPS-203) and ML-DSA (FIPS-204).
IP Cores, Inc., California, USA had announced modifications to its true random number generator IP core, TRNG1.
IP Cores, Inc. has announced that the first shipment of the server memory encryption IP cores occurred one year ago.
IP Cores, Inc., (California, USA, http://www.ipcores.com) has announced modifications of its MSP10-512 cores that support line-speed MACsec encryption and decryption for the 400 Gbps Ethernet.