AHB AES with DMA
The Encryption Standard (AES) IP Core is a hardware implementation encryption/decryption algorithm described in the U.S.
Overview
The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government Federal Information Processing Standards Publication 197 (FIPS 197). The AES IP Core implements the Rijndael algorithm which is a symmetric block cipher that can process 128-bit data blocks using 128, 192, or 256-bit cipher keys. The United States Government designed the Advanced Encryption Standard (AES) in 2000 to replace the older Data Encryption Standard (DES). AES is a symmetric block cipher which means that the same key is used for both encryption and decryption of the data block.
The AHB AES Encryption/Decryption Engine is a configurable core that interfaces to an AHB microprocessor bus. To accommodate a wide variety of system requirements, the Engine can be generated in one of three configurations: Low Gates, Mid Gates and High Gates.
The register interface of the AHB AES Engine is accessed via an AHB Slave component interface. Once the Engine has been configured and enabled, an AHB Master component interface is used to transfer data to/from system memory using DMA transfers. The core reads from a programmable source location in system memory into an internal Input FIFO, performs the desired action (encryption or decryption) on the data and stores the result in an internal Output FIFO. Lastly, the contents of the Output FIFO are written to a programmable destination location in system memory.
A maskable interrupt can be enabled to notify the processor when all DMA transfers are complete, and the output data has been transferred to system memory.
Key features
- Advanced Encryption Standard FIPS 197 compliant
- Implements Rijndael algorithm
- Efficient “Tower Field” SBox implementation
- Encrypts / Decrypts 128 bit data blocks
- Supports key lengths of 128, 192, and 256 bits
- AHB Master component Interface for DMA memory transfers to and from the AES Engine
- AHB Slave component Interface for control/status register access
- AES Modes Supported
- Electronic Code Book (ECB)
- Cipher Block Chaining (CBC)
- Output Feedback (OFB)
- A maskable interrupt condition is supported
- Multiple AES Engine configurations
- Low Gates (lowest gate count, slow performance)
- Mid Gates (faster performance)
- High Gates (highest performance)
Block Diagram
What’s Included?
- Verilog Source
- Complete Test Environment
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Security
Provider
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Frequently asked questions about Symmetric Cryptography IP cores
What is AHB AES with DMA?
AHB AES with DMA is a Symmetric Crypto IP core from Silvaco, Inc. listed on Semi IP Hub.
How should engineers evaluate this Symmetric Crypto?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.