DDR2 PHY IP Listing

DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process

• UMC
• 130nm
• HS
• In Production

DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process

• UMC
• 130nm
• HS
• Silicon Proven

DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process

• UMC
• 130nm
• HS
• In Production

DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process

• UMC
• 130nm
• HS
• Pre-Silicon

DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process

• UMC
• 55nm
• SP
• Silicon Proven

DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process

• UMC
• 65nm
• Silicon Proven

The DDR3/2 PHY is compatible with JEDEC DDR3 and JEDEC DDR2 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to1866Mbps …

• UMC
• 40nm
• LP
• In Production

The DDR multiPHYs are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 S…

• Single-Protocol PHY
• Silicon Proven
• Immediate

This DDR PHY IP(Double Data Rate) supports DRAM type DDR3, DDR3L this PHY provides low latency, and enables up to 1600Mbps throug…

• UMC
• 40nm
• LP
• In Production

The DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3 and DDR2 SDRAM memor…

• TSMC
• 40nm
• LP

The DDR3/2 PHY is a mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design ta…

• Single-Protocol PHY
• Silicon Proven
• Immediate

DDR2 SDRAM Controller

• DDR
• now
• Supports industrial standar…

Synopsys offers a system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performanc…

• DDR
• Available on request
• Available

Synopsys offers a system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performanc…

• DDR
• Available on request
• Available

Increasing SoC/ASIC devices' complexity also demands increase in memory bandwidth.

• DDR
• In volume production silicon
• Now
• DDR1, DDR2, DDR

DDR2 DFI Verification IP provides an smart way to verify the DDR2 DFI component of a SOC or a ASIC.

• Verification IP

DDR2 DFI Assertion IP provides an efficient and smart way to verify the DDR2 DFI designs quickly without a testbench.

• DDR

The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…

• DDR

The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…

• DDR

The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…

• DDR