How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
T2M GmbH
Category:
DDR
DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)
The DDR3/2 PHY is compatible with JEDEC DDR3 and JEDEC DDR2 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to1866Mbps …
Overview
The DDR3/2 PHY is compatible with JEDEC DDR3 and JEDEC DDR2 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to1866Mbps and DDR2 DRAM speeds from 666Mbps to 1066Mbps, and target support x16 DDR3/DDR2 SDRAM components, the design include an analog hard macro (CLK/CMD/ADDR/DQ/DQS) and a synthesizable digital design. it supports software auto training includes read gate, read/write data eye timing.
The DDR IP is silicon proven. The PHY is optimized for high performance, low latency, low area, low power, ease of integration and faster time-to-market.
The DDR IP is silicon proven. The PHY is optimized for high performance, low latency, low area, low power, ease of integration and faster time-to-market.
Key features
- Supports DDR3/DDR2 SDRAM
- DDR3 JEDEC standard 1.5v I/O (SSTL_15- compatible)
- DDR2 JEDEC standard 1.8v I/O (SSTL_18- compatible)
- 16 bits width, Single Channel DDR3/DDR2 SDRAM Interface.
- 16 bits for per channel, could support 2 x8 bits DDR3
- Memory Clock up to 466MHz, DFI Clock up to 466MHz.
- Support DDR3 800/1066/1333/1600/1866Mbps; DDR2 800/1066Mbps
- Supports DFI like interface
- Supports Continuous Request
- 4-bit pre-fetch architecture
- DLL Lock for 933MHz
- Supports SW DDR training
- Supports DDR IO loopback test
- Providing per bit de-skew function
- Programmable DQS, DQS# Read/Write offset
- Programmable CS, MA ,CK/CK#, ODT offset
- Supports DDR3 DLL disable mode (CL6/CWL6)
- Supports DDR3/DDR2 CL=5 ~ CL17
- Supports DDR3/DDR2 CWL=5, CWL=11
- Supports DDR3 Read eye training
- Supports DDR3 Write eye training
- Supports DDR2 Read gated training
- Supports DDR2 Read eye training
- Supports DDR2 Write eye training
- Supports DDR3 Retention mode
- Supports DQ TX/RX per-bit deskew
- 0.9V Core Power supply
- 1.5V DDR3 IO Power supply
- 1.8V DDR2 IO Power supply
- Support software DDR training
- DDR3 training : support RX_GATED training, perbit de-skew for RX/TX path, DQ RX eye training and DQ TX eye training
- DDR2 training : support RX_GATED training, perbit de-skew for RX/TX path, DQ RX eye training and DQ TX eye training
Block Diagram
DDR3/ DDR2 Combo PHY IP in 40LP block diagram
Benefits
- 16 bits for per channel, could support 2 x8 bits DDR3
- Memory Clock up to 466MHz, DFI Clock up to 466MHz
- Support DDR3 800/1066/1333/1600/1866Mbps; DDR2 800/1066Mbps
- Supports DDR3 Retention mode
- Supports DDR3 Burst length 4/8
- Supports DFI like interface
- Supports Continuous Request
Applications
- SSD Controller
- Digital TV
- Mobile
- Multimedia
- Setup Box
- Data centers (networking and storage)
- Servers
- High-performance computing
- IOT
- Surveillance
What’s Included?
- User Manual
- Behavior model, and protected RTL codes
- Protected Post layout netlist and Standard
- Delay Format (SDF)
- Frame view (LEF)
- Metal GDS (GDSII)
- Test patterns and Test Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 40nm | LP | In Production |
Specifications
Identity
Part Number
DDR3/ DDR2 Combo PHY IP in 40LP
Vendor
T2M GmbH
Type
Silicon IP
Controller / PHY
Controller + PHY
,
PHY
Standards & Interfaces
Memory
DDR2
,
DDR3
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Germany
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
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Frequently asked questions about DDR Interface IP
What is DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)?
DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP) is a DDR IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for umc In Production.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.