How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Synopsys, Inc.
Category:
DDR
Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive
The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
Overview
The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uMCTL2), and the Enhanced Universal DDR Protocol Controller (uPCTL2). Both products support the JEDEC DDR4, DDR3, DDR2, Mobile DDR, LPDDR4, LPDDR3, and LPDDR4 SDRAM standards and AMBA AXI3/AXI4 and native on-chip busses. Both products have extensive features for low power and high Reliability, Availability and Serviceability (RAS).
The uMCTL2 Memory Controller incorporates a scheduler and optional arbiter to serve memory requests from 1-16 application-side host ports with high bandwidth and low latency that is managed by Quality of Service (QoS) mechanisms.
The uPCTL2 Protocol Controller serves the needs of applications where scheduling is done in the interconnect or elsewhere on the host side, providing low latency and in-order command execution.
All the Universal controllers connect to PHYs via the industry-standard DFI interface, and all their registers may be accessed through industry-standard APB busses.
Key features
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
- Multichannel and Shared Address/Command (Shared AC) configuration options
- Boot-time programmable frequency ratio
- Data rates up to 4266 Mbps in 1:2 frequency ratio, using a 1067 MHz controller and 2133 MHz memory clock (Dependent on process and PHY chosen)
- Data rates up to 3200 Mbps in 1:2 frequency ratio, using an 800 MHz controller clock and 1600 MHz memory clock (Dependent on process and PHY chosen)
- Data rates up to 1600 Mbps in 1:1 frequency ratio, using an 800 MHz controller clock and 800 MHz memory clock (Dependent on process and PHY chosen)
Block Diagram
dwc_ap_ddr_umctl2p block diagram
Specifications
Identity
Part Number
dwc_ap_ddr_umctl2p
Vendor
Synopsys, Inc.
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR2
,
DDR3
,
DDR4
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about DDR Interface IP
What is Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive?
Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive is a DDR IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.