5G IP Listing

IGAAFEV03A is a high speed analog front-end circuit for 5GNR application which supports 4T4R.

• TSMC
• 12nm
• FFC
• Pre-Silicon

This PHY IP supports both USB 3.1 Gen1 & Gen2.

• USB 3.1
• TSMC
• 28nm
• HPC+
• In Production

With this PHY IP, it supports both USB 3.1 Gen1 and Gen2.

• USB 3.1
• SMIC
• 14nm
• SF+
• In Production

It supports both USB 3.1 Gen1 and Gen2 with this PHY IP.

• USB 3.1
• UMC
• 28nm
• HPC
• In Production

The full gamut of PCIe 2.0 Base operations is covered by PCIe 2.0 transceiver IP.

• UMC
• 40nm
• LP
• In Production

The CL12842M8RM3AM5AIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) …

• TSMC
• 12nm
• FFC
• Silicon Proven

The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum.

• USB
• Available on request
• Available

USB 3.0 OTG Controller IP is based on the latest USB 3.0 specification from USB Implementer Forum (USBIF) and is compatible with…

• USB
• In Production
• Immediate
• USB3.0 specification Revisi…

Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps.

• MIPI
• New product
• Now
• MIPI CSI2, MIPI DPHY

Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps.

• MIPI
• New Product
• Mow
• MIPI CSI2 MIPI DPHY AMBA APB

USB3.0 SuperSpeed Device The Super Speed USB bus is implemented as a separate dual-simplex data path consisting of two uni-direct…

• USB
• Complies w ith USB 3.0 stan…

The MAC core for Wireless LAN is compatible with 802.11 a b and g IEEE Standards.

• Wi-Fi
• now
• Fully Compliant to IEEE 802…