Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
GF L12LP 12nm Deskew PLL - 400MHz-2000MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
GF L12LP 12nm Deskew PLL - 800MHz-4000MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
GF L12LP 12nm DDR DLL - 188MHz-940MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LP 12nm DDR DLL - 250MHz-1250MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LP 12nm DDR DLL - 395MHz-1975MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LP 12nm Clock Generator PLL - 200MHz-1000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
GF L12LP 12nm Clock Generator PLL - 400MHz-2000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
GF L12LP 12nm Clock Generator PLL - 800MHz-4000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
PCIe 7.0 Integrity and Data Encryption (IDE) Security IP Module
PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to …
The ONFI IP provides Turnkey solutions for IC requiring access to ONFI-compatible NAND Flash devices.
The’s I3C (Improved Inter Integrated Circuit) is enhanced with I2C protocol and is compatible with I2C.
BGR + V-I Bandgap Reference Circuit
HCLTech offers IP Bandgap (BGR) bgr_1p2_t40_v1 generates precision reference voltage (0.4V ~ 1.2V) and current reference (1.005µA…
HCLTech offers IP RC Oscillator core consists of digital to analog current converter [IDAC], Ring Oscillator and Level shifter.
HCLTech offers SAR ADC 10bit hcl_saradc_10bit_5msps_t40_v1 is a general-purpose analog to digital converter (ADC).
HCLTech offers IP Temperature Sensor hcl_tempsense_t40_v1 (temperature sensor IP) utilizes a Proportional to Absolute Temperature…
HCLTech offers IP POR hcl_por_t40_v1 circuit provides a reset signal to the chip when supply ramps up so that the chip always sta…
HCLTech offers A low drop-out (LDO) voltage regulator has been designed in a 40nm tsmc technology.
HCLTech Offers IP Process Monitor IP (hcl_procmon_t40_v2) consists of three ring oscillators namely RVT Ring Oscillator, Thick ox…
The AHB to APB bridge is an AHB slave, providing an interface between the highspeed AHB and the low-power APB.
Watchdog Timer IP is used to monitor status of Host.