UPF Constraint coding for SoC - A Case Study
This paper deals with the implementation of UPF for low power SoC design that can encompass several vendor IPs and custom IPs UPF constraints.
Vendor:
HCL Technologies
Category:
Power On Reset (POR)
Power On Reset (POR)
HCLTech offers IP POR hcl_por_t40_v1 circuit provides a reset signal to the chip when supply ramps up so that the chip always sta…
Overview
HCLTech offers IP POR hcl_por_t40_v1 circuit provides a reset signal to the chip when supply ramps up so that the chip always starts in a known state. It ensures that stable and adequate supply voltages are available to the circuit. The hcl_por_t40_v1 is implemented in a tsmcN40 CMOS process.
If POR CORE circuit fails (stuck at either zero or VDD), then to power up the chip an external bypass signal is needed. Hence an additional dedicated BYPASS block is provided to bypass POR CORE circuit.
Hcl_por_t40_v1 architecture also has a TEST MODE CIRCUITS block which consists of circuits which are used to enable and generate A_TESTOUT from different outputs of POR CORE circuit.
If POR CORE circuit fails (stuck at either zero or VDD), then to power up the chip an external bypass signal is needed. Hence an additional dedicated BYPASS block is provided to bypass POR CORE circuit.
Hcl_por_t40_v1 architecture also has a TEST MODE CIRCUITS block which consists of circuits which are used to enable and generate A_TESTOUT from different outputs of POR CORE circuit.
Key features
- Provides BYPASS mode.
- Minimum Reset delay of 2.782 µs. (at RC-Worst)
- Rising threshold voltage: Maximum of 1.57V(at RC-Worst, RC-Best)
- Falling threshold voltage: Minimum of 1.25V. (at RC-Worst, RC-Best)
- Hysteresis voltage: Minimum of 70mV. (at RC-Worst, RC-Best)
- Brownout detection duration: 11.05 µs. (at RC-Worst corner)
- Quiescent current: Maximum of 11.2 µA.
- Area of 156.2*88.3 sq. µm.
Block Diagram
HCLTech_por_t40_v1 block diagram
Applications
- RCOSC,
- DIGITAL CORE,
- Analog IP A(example: RF ADC),
- Analog IP B(example: DAC)
- Default trim + level shifter.
- JTAG
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 40nm | G | — |
Specifications
Identity
Part Number
HCLTech_por_t40_v1
Vendor
HCL Technologies
Type
Silicon IP
Provider
HQ:
India
Learn more about Power On Reset (POR) IP core
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Frequently asked questions about Power-On Reset (POR) IP cores
What is Power On Reset (POR)?
Power On Reset (POR) is a Power On Reset (POR) IP core from HCL Technologies listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this Power On Reset (POR)?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power On Reset (POR) IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.