Learn more about PCIe / CXL IDE IP core
Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.
After more than three decades, the relationship between Arm and Synopsys continues to redefine the semiconductor industry. And the fusion of our expertise and technology continues to reshape chip design flows.
This article delves into the technical aspects of how scaling up and out is becoming a critical need for HPC and AI chip developers, and how new standards such as Ultra Ethernet and Ultra Accelerator Link (UALink) aim to tackle the challenges of high-bandwidth, low-latency connectivity and efficient resource management.
Richard Solomon, Synopsys