LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams.
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in UMC 65/55ULP
The HDMI receiver PHY (Physical layer), a single-port IP core, complies fully with HDMI 1.4's requirements.
Our MIPI-D-PHY IP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI Alliance Sta…
The demand for multimedia features are pushing device manufacturers to integrate more peripherals such as multi-megapixel cameras…
HDMI transmitter PHY (Physical layer) IP core which is fully amenable with HDMI 1.4/2.0 specification.HDMI transmitter PHY which …
The LVDS transceiver IP is a SERDES pair that clearly interprets 12–bit parallel bus into serial stream.
HDMI 2.1 Tx- Rx PHY & Controller IP (Silicon Proven in TSMC 28HPC+)
The HDMI V2.1 Tx provides a single-link HDMI transmitter function complies with HDMI specification version 2.1.
USB 3.0 Gen1 / Gen2 Host Controller IP
We provide configurable and scalable USB 3.1 host/device/dualmode controller IP Cores for a wide range of applications.
The Synopsys SuperSpeed USB IP solution is implemented in hundreds of designs and shipped in millions of units.
DDR4/3 PHY in TSMC (12nm, 16nm, 7nm)
The Synopsys DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC)…
DDR4/3 PHY in Samsung (14nm, 11nm, 10nm, 8nm)
The Synopsys DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC)…
USB 2.0 picoPHY in UMC (40nm, 28nm)
The Synopsys USB 2.0 picoPHY provides designers with a physical (PHY) layer IP solution, designed for low power mobile and consum…
USB 2.0 picoPHY in TSMC (40nm, 28nm)
The Synopsys USB 2.0 picoPHY provides designers with a physical (PHY) layer IP solution, designed for low power mobile and consum…
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm)
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
USB 2.0 nanoPHY in SMIC (65nm)
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
IP
This datasheet describes GUC’s HBM (High Bandwidth Memory) PHY IP, which can be integrated with HBM memory controller to provide …
and cost-efficient scalable platform from low to (very) high end True SDR Processor World-Wide Receiver Upgradable Prepared for t…
24-bit Cap-less ADC PLL-less 2 channels
The sADC-H1-LR.02 is a mixed (analog and digital) Virtual Component containing 2 mono ADCs, and additional functions offering an …