MIPI-M-PHY IP

The demand for advanced multimedia features are pushing device manufacturers to integrate more advanced peripherals such as multi-megapixel cameras and larger screens. Integrating these capabilities into next-generation devices brings new challenges to the industry in terms of power, time-to-market and overall system costs.
To address these challenges, the Mobile Industry Processor Interface (MIPI®) Alliance defines and promotes open interface specifications, such as the Camera Serial Interface (CSI-2), Display Serial Interface (DSI), which all use the MIPI D-PHY.
MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing to your pads.
The D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.

The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for high-Speed data traffic while low power functions are mostly used for control. In HS mode, the low swing differential signal is able to support data transfers from 80 Mbps to 1.5 Gbps. In LP mode all wires operate as a single-ended line capable of supporting 10 Mbps asynchronous data communications. The D-PHY is a complete PHY, silicon-proven at multiple foundries.