The Synopsys DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications req…
- Controller + PHY + 1
- DDR5
- GlobalFoundries
- 12nm
- LP
- Available on request
The Synopsys DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications req…
DDR5/4 PHY in TSMC (16nm, 12nm, N6, N7, N5)
The Synopsys DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications req…
The Synopsys DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications req…
The Synopsys DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications req…
USB 2.0 picoPHY in GF (40nm, 28nm)
The Synopsys USB 2.0 picoPHY provides designers with a physical (PHY) layer IP solution, designed for low power mobile and consum…
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
USB 2.0 femtoPHY in GF (28nm, 22nm, 12nm)
The Synopsys IP USB 2.0 femtoPHY provides designers with a physical (PHY) layer IP solution for low-power mobile and consumer app…
USB 2.0 femtoPHY in GF (22nm) for Automotive Grade 1
The Synopsys IP USB 2.0 femtoPHY provides designers with a physical (PHY) layer IP solution for low-power mobile and consumer app…
USB 2.0 femtoPHY in TSMC (16nm, N7) for Automotive
The Synopsys IP USB 2.0 femtoPHY provides designers with a physical (PHY) layer IP solution for low-power mobile and consumer app…
USB2.0 PHY(HSIC/Host/Device/OTG/Hub)/ eUSB PHY
USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications.
LPDDR4X/4/3/DDR4/3/3L PHY & Controller
The DDR IP Mixed-Signal MR LPDDR4X/4/3/DDR4/3/3L Combo PHY provides turnkey physical interface solutions for ICs requiring access…
TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY
IGPD2DZO1A is a high-speed Die-to-Die interface PHY that transmits data through TSMC packaging solutions, Integrated Fan-Out (InF…
Ultra-short reach SerDes with 500 Gbit/s throughput
High-density, low-power SerDes IP delivering 500 Gbit/s throughput for in-package and multi-chip module interconnects, without a silicon interposer.
Unleash the power of precision and innovation with the NS_TX_16G_T16, a 12-bit, 16-Gsps Digital-to-Analog Converter (DAC) array.
Unleash the power of precision and innovation with the NS_RX_12G_T16, a 12-bit, 12-Gsps Analog-to-Digital Converter (ADC).
32G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 22nm
Designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G The 32…
MIPI D-PHY Rx IP, Silicon Proven in GF 55LP
Version 1.2 of the D-PHY specification is fully complied with by the MIPI D-PHY Analog RX IP Core.
The MAN_CODEC IP Core is a versatile encoder and decoder pair that converts a basic NRZ bitstream into a standard Manchester code…
MSquare offers a silicon-proven ONFI 5.0 PHY IP that supports all modes of the Open NAND Flash Interface (ONFI) 5.0 specification.
MSquare's HBM3 IP (the 3rd generation of High-Bandwidth Memory) is specifically tailored for applications that require high memor…