MIPI MDDI PHY IP Listing

MIPI  DSI2

• MIPI

MIPI CSI-2

• MIPI

The MIPI D-PHY Analog TX IP Core adheres fully to version 1.2 of the D-PHY specification.

• MIPI D-PHY
• TSMC
• 22nm
• ULP
• In Production

The MIPI DSI-2 controller core is optimized for high performance, low power and small size.

• MIPI
• Now

The MIPI CSI-2 controller core is optimized for high performance, low power and small size.

• MIPI
• Now

Our silicon proven Automotive IP Suite offers versatile and robust IP solutions for high-speed data communication in automotive a…

• System Controller

The D-PHY specification, version 1.2, is completely complied with by the MIPI D-PHY Analog TX IP Core.

• MIPI D-PHY

The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification.

• MIPI D-PHY
• TSMC
• 40nm
• LP
• In Production

The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification.

• MIPI D-PHY
• SMIC
• 55nm
• LL
• In Production

UniPro (Unified Protocol) is a layered protocol defined by the MIPI Alliance for connecting devices and components within a mobil…

• UFS Controller
• In Production
• Immediate
• MIPI UniPro Standard V1.6 a…

Version 1.2 of the D-PHY specification is completely complied with by the MIPI D-PHY Analog TX IP Core.

• MIPI D-PHY
• TSMC
• 28nm
• HPC+
• In Production

Brite provides full solution for the MIPI CSI interface, which receives the data from sensors in PHY layer, and then converts the…

• MIPI

The MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI®…

• MIPI D-PHY

MIPI RX PHY is a mass production IP for D-PHY v1.2 and C-PHY v1.2 protocols.

• MIPI PHY
• Mass Production

This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.

• MIPI C-PHY

Our MIPI CD-PHY Transmitter and receiver PHY with Display Serial Interface (DSI) and Camera Serial Interface (CSI) Controllers ar…

• MIPI C-PHY

The MIPI D-PHY RX 2/4 Lanes macro implements the physical layer of universal lanes for the MIPI D-PHY interface, stacked in a two…

• MIPI D-PHY

The MIPI D-PHY Bidirectional 2-Lane(4-Lane) macro implements the physical layer of bidirectional universal lanes for the MIPI D-P…

• MIPI D-PHY

The MIPI-LVDS Combo Tx IP is designed for chips that perform high bandwidth data communication while operating at low power consu…

• SMIC
• 40nm
• LL
• In Production

IP

• MIPI D-PHY