What is ACU200 Sensor Computing IP?
ACU200 Sensor Computing IP is a DSP Core IP core from Acute Design listed on Semi IP Hub.
Vendor:
Acute Design
Category:
DSP Core
ACU200 Sensor Computing IP
Programmable multicore signal-processing IP combining continuous sample-based processing with concurrent block-based computation.
Overview
ACU200 is a programmable real-time sensor computing IP under development. It combines low-latency sample-based streaming with block-based computation and enhanced multicore parallelism. Streaming and block workloads can run concurrently and exchange data and runtime parameters, enabling audio, biosignal and heterogeneous sensor preprocessing close to the sensor I/O.
ACU200 Specifications
|
Attribute |
Specification |
|
IP type |
Preliminary scalable sensor-computing subsystem |
|
Compute |
Multicore 32-bit RISC-V; Zfinx-based FP32 and signal-processing extensions |
|
Execution |
Concurrent sample-based streaming and block-based processing |
|
Parallelism |
Node, channel, pipeline, block and supported kernel-level parallelism |
|
Memory and buffering |
Configurable TCDM/TCPM, banking, queues and stream/block buffers |
|
Sensor interfaces |
PCM/PDM, generic ready/valid streams and memory input/output |
|
Host integration |
Memory/MMIO access, AHB or AXI host-bus options and event synchronization |
|
Performance scope |
Workload- and configuration-dependent; no numerical benchmark is asserted here |
These are preliminary architecture capabilities. Resource options, supported kernels and timing depend on the implementation option and SDK release. Numerical rate, latency, area and power benchmarks are not asserted here.
Availability and validation
|
Status |
Description |
|
Availability |
Ready to be evaluated. Preliminary SDK available to selected target customers; implementation remains under development. |
|
Completed validation |
Completed RTL verification is not declared for ACU200. |
|
Current milestone |
Feature set frozen. |
|
Planned milestones |
Contact ACUTE Design for implementation and software roadmap information; no public dates are stated here. |
Key features
- Concurrent sample-based and block-based graphs, with resource allocation for each workload.
- Scalable 32-bit RISC-V cluster with Zfinx-based IEEE-754 FP32 and FFT-oriented signal-processing extensions.
- Parallel execution across nodes, channels, pipeline stages, blocks and supported kernels.
- Configurable TCDM/TCPM, stream queues, block accumulation and ping-pong or circular buffering.
- PCM, PDM, generic ready/valid streams and memory streams; Python graph flow and runtime reconfiguration.
Block Diagram
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Benefits
A continuous low-latency audio path can remain active while other compute resources run block-based adaptation or analysis. Adaptive results can update coefficients in the active graph, while feature or monitoring data moves to the host. One programmable subsystem can prepare heterogeneous streams for downstream CPU, DSP or NPU processing. As a fully digital IP, ACU200 is independent of any specific process technology or foundry, giving customers the freedom to choose the manufacturing platform that best fits their product requirements.
Applications
Adaptive ANC and beamforming front ends, hearing devices, smart glasses, ear-EEG and other biosignal wearables, multimodal sensor hubs and line- or block-oriented sensor preprocessing.
What’s Included?
Deliverables include an IP integration package, supporting technical documentation and a software development kit (SDK).
The SDK includes the compiler toolchain, graph development and configuration tools, runtime support and processing libraries. A bit-accurate virtual platform enables developers to develop, simulate and functionally validate their application software and processing graphs.
The IP delivery format and package scope are agreed according to each project’s requirements.
Specifications
Identity
Part Number
ACU200
Vendor
Acute Design
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
France
Frequently asked questions about DSP Core IP cores
How should engineers evaluate this DSP Core?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DSP Core IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.