VeriSilicon Microelectronics (Shanghai) Co., Ltd. (VeriSilicon, 688521.SH) is a leading public company that provides custom silicon solutions, leveraging its comprehensive and proprietary portfolio of semiconductor IPs.
VeriSilicon possesses six categories of in-house processing IPs, namely Graphics Processing Unit (GPU) IP, Neural Network Processing Unit (NPU) IP, Video Processing Unit (VPU) IP, Digital Signal Processing (DSP) IP, Image Signal Processing (ISP) IP, and Display Processing IP, as well as more than 1,700 analog and mixed-signal IPs, RF IPs, and interface IPs.
Leveraging its own IPs, VeriSilicon has developed a wealth of software and hardware custom chip design platforms targeting Artificial Intelligence (AI) applications, covering always-on ultralight spatial computing devices such as smartwatches and AI/AR glasses, high-efficiency edge computing devices such as AI PCs, AI phones, smart cars, and robots, as well as high-performance cloud computing devices like data centers and servers.
In response to the trend of System-on-Chip (SoC) evolving towards System-in-Package (SiP) driven by the demand for large computing power, VeriSilicon put forward the concepts of "IP as a Chiplet”, "Chiplet as a Platform", and "Platform as an Ecosystem”. The company keeps advancing the R&D and industrialization of its Chiplet technologies and projects from the perspective of interface IP, Chiplet architecture, advanced packaging technology, and others for AI-Generated Content (AIGC) and autonomous driving solutions.
Under its unique “Silicon Platform as a Service” (SiPaaS) business model, VeriSilicon serves a broad range of market segments, including consumer electronics, automotive electronics, computer and peripheral, industrial, data processing, Internet of Things (IoT), among others. Its main customers include fabless, IDM, system vendors (OEM/ODM), large internet companies, and cloud service providers.
Founded in 2001 and headquartered in Shanghai, China, VeriSilicon has 9 design and R&D centers, along with 11 sales and customer service offices worldwide. VeriSilicon currently has more than 2,000 employees.
USB 3.0 and PCIe 2.0 Combo PHY
The USB 3.0 SuperSpeed and PCI Express Combo PHY is a programmable IP compatible with the PHY Interface for the PCI Express Archi…
The embedded USB 2.0 (eUSB2) PHY is a high-speed System-on-Chip (SoC) integrated transceiver IP in process that implements the In…
1.25 Gbps-16 Gbps HSS for Supporting Multiple Protocols
The 12.5 Gbps to 16 Gbps high-speed SerDes (HSS) is compatible with multiple industry protocols.
1.25 Gbps-12.5 Gbps HSS for Supporting Multiple Protocols
The 1.25 Gbps to 12.5 Gbps high-speed SerDes (HSS) is compatible with multiple industry protocols.
DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a RX PHY
The DP/eDP Combo RX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a.
DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a TX PHY
The DP/eDP Combo TX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a.
HDMI RX PHY is the physical layer of a single-port HDMI transmitter interface.
HDMI TX PHY is the physical layer of a single-link HDMI transmitter interface.
VBO Receiver with four and eight lanes for video communication
VBO Transmitter with 8 lanes and 16 lanes for video communication
UCIe Controller (CHI Protocol + Adapter)
The UCIe Controller consists of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layers.
UCIe Controller (AXI Protocol + Adapter)
The UCIe Controller consists of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layers.
Die-to-Die (D2D) Interface for Chiplet Application
Compliant with the UCIe Specification Revision 1.1
Cost-efficiency, AI-based noise reduction IP
The AI-NR series IPs offer noise reduction solutions for optimizing image quality in low-light or complex lighting conditions.
High-efficiency, AI-based super resolution IP
The AI-SR series IPs offer super resolution solutions for enhancing video quality and pixel resolution, primarily used for post-p…
The USB 3.2 SuperSpeed Plus PHY provides a range of USB 3.2 Gen2 host and peripheral applications at up to 10 Gbps per lane, whic…
The USB 2.0 PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
Physical Layer Interface for SD and eMMC Storage Devices
Physical Layer of LVDS Receiver
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…