The Power-On Reset (POR) and Over Current Detection (OCD) macro comprehensively addresses typical SOC start-up power supply monit…
- TSMC
- 5nm
- N5A
Analog Bits develops, delivers and supports industry-leading, mixed signal IP solutions. The current product portfolio includes energy-efficient and low-area SERDES, PVT sensors, ultralow-jitter clocks, memory interfaces and I/O’s, available on every mainstream manufacturing process. Customers’ applications span a wide range including: high-volume consumer products, energy-efficient servers and advanced telecommunications equipment - all leveraging Analog Bits’ highly differentiated IP products.
Founded in 1995, Analog Bits, Inc. has become the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs. Our products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s as well as specialized memories such as high-speed SRAMs and TCAMs. With billions of IP cores fabricated in customer silicon, from 0.35-micron to 14-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.
The Power-On Reset (POR) and Over Current Detection (OCD) macro comprehensively addresses typical SOC start-up power supply monit…
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
Power On Reset on TSMC CLN28HPC+
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
Power On Reset on TSMC CLN28HPC
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
Power On Reset on TSMC CLN16FFC
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
Power On Reset on TSMC CLN12FFC
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
Power On Reset on GLOBALFOUNDRIES 12LP+
The Power-On Reset (POR) and Over Current Detection (OCD) macro comprehensively addresses typical SOC start-up power supply monit…
Power On Reset on GLOBALFOUNDRIES 12LP
The Power-On Reset (POR) and Over Current Detection (OCD) macro comprehensively addresses typical SOC start-up power supply monit…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN7FF
The PCIe Gen5 REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN6FF
The PCIe Gen5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN3P-CLN3X
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN3E
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen4/5 Ref Clock SSCG PLL on GLOBALFOUNDRIES 12LP+
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen3 Class SSCG PLL on TSMC CLN16FFC
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Gen3 Class SSCG PLL on TSMC CLN12FFC
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Gen3 Class SSCG PLL on GLOBALFOUNDRIES 12LP+
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Gen3 Class SSCG PLL on GLOBALFOUNDRIES 12LP
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…