Vendor: Analog Bits Inc. Category: PLL

Jitter Cleaning PLL on TSMC CLN40G

The Jitter Cleaning PLL macro is implemented in Analog Bits’ proprietary architecture that uses 0.9V core and 1.8V IO oxide devic…

TSMC 40nm G View all specifications

Overview

The Jitter Cleaning PLL macro is implemented in Analog Bits’ proprietary architecture that uses 0.9V core and 1.8V IO oxide devices. The PLL macro uses two clean externally filtered analog supply voltages at 0.9V and 1.8V, and up to 3 extra pads and additional on-package capacitors. The output clock is set to multiply by 8, (FOUT = FREF x 8). PLL divider ratios are to be set appropriately based on value of FREF to keep FVCO ≈ 14GHz. This is to limit the operating range of the VCO and to allow fine-tuning the VCO for best jitter/phase-noise performance (please see section “PLL Divider Settings”). The PLL is self-calibrated by the de-assertion of PLL_RESETB.

The relationships between the different frequencies of the PLL are as follows: FOUT = FREF x 8 FVCO = FREF x 8 x DDIVO2 x 4 In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. The PLL macro is designed for implementation in a flip-chip package.

Key features

  • Electrically Programmable PLL for high fidelity clocking applications
  • Excellent jitter and phase noise performance
  • Produces output clock of FOUT = 8 X FREF
  • Implemented with Analog Bits’ proprietary architecture
  • Uses two analog supplies
  • Low power consumption

Silicon Options

Foundry Node Process Maturity
TSMC 40nm G —

Specifications

Identity

Part Number
Jitter Cleaning PLL on TSMC CLN40G
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PLL IP core

Analog Bits to Participate in a Customer Test Chip Tapeout on TSMC A14 and Present Papers with Cerebras, Arm and Socionext on Real-Time On-Chip Power Sensing and Delivery at 2026 TSMC Global OIP Ecosystem Events

At TSMC 2026 North America OIP Ecosystem Forum, Analog Bits will showcase new real-time power observability and sensing analog IP in TSMC’s N2P process technology and present a paper with Cerebras; Papers planned with partners at global OIP Ecosystem events to highlight smarter power delivery for scalable SoCs targeting data centers, automotive and more.

Frequently asked questions about PLL IP cores

What is Jitter Cleaning PLL on TSMC CLN40G?

Jitter Cleaning PLL on TSMC CLN40G is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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