Low Jitter PLL on TSMC CLN7FF

The Low Jitter PLL creates a high quality clock with good duty cycle and jitter characteristics useful for source synchronous interfaces and other low jitter applications. The PLL is designed in a standard digital logic process and uses robust design techniques including an integrated LDO (Low Drop Out regulator) to work in typical SoC environments.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power.

PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 1300 2000 MHz VCO Frequency FVCO 10000 16000 MHz Output Frequency FOUT 2500 8000 MHz Output Duty Cycle tDO -4 ±2 -4 ps Lock Time tLOCK 70 µs Reset Time tRESET 1 µs 600fs-RMS @10GHz (with integration band Long Term Random Jitter RJ from 1GHz to Nyquist) Total area of macro A 0.012 sq.mm Dimensions: 117um (X) by 100um (H) Total Power (unloaded) IDD 15.8 mW Output Load CL 50 fF Operational Voltage (Digital) VDIG 0.675 0.75 0.825 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V Operational Temperature TOP -40 25 125 C

• Electrically Programmable PLL for multiple applications
• Wide Ranges of Output Frequency for diverse clocking needs
• Implemented with Analog Bits’ proprietary architecture
• Low power consumption
• Integrated LDO to reduce deterministic jitter
• Spread Spectrum tracking capability
• Requires no additional on-chip components or band-gaps, minimizing power consumption
• Excellent jitter performance with optimized noise rejection