100% Secure Cryptographic System for RSA, Diffie-Hellman and ECC with AMBA AHB, AXI4 and APB
CryptOne is a fully scalable, hardware-accelerated cryptographic system built on 20+ years of DCD-SEMI’s engineering experience.
- RSA
Founded in 1999, Digital Core Design is a global leader in IP core development, specializing in microprocessor, microcontroller, and communication solutions. With a portfolio of over 100 IP cores, DCD continues to drive innovation in embedded systems, providing cutting-edge solutions for automotive, industrial, IoT, and security applications.
100% Secure Cryptographic System for RSA, Diffie-Hellman and ECC with AMBA AHB, AXI4 and APB
CryptOne is a fully scalable, hardware-accelerated cryptographic system built on 20+ years of DCD-SEMI’s engineering experience.
EdDSA Curve25519 signature generation engine
EdDSA IP Core — When Safety and Security Meet the Best Size/Performance Ratio The EdDSA Curve25519 extension adds hardware suppor…
The D68000-CPU32+ soft core is binary-compatible with the industry standard 68000’s CPU32+ version of the 32-bit microcontroller.
Hash and HMAC Functions Accelerator
The DSHA2-384 - a universal solution that accelerates SHA2-384 hash with HMAC mode.
Enhanced Serial Peripheral Interface – Target IP with single, dual, and quad eSPI Bus support for Intel CPU’s
SHA IP Core with native SHA2-256 HMAC support
The DSHA2-256 is a universal solution which efficiently accelerates SHA2-256 hash function compliant with FIPS PUB 180-4.
Scalable & Royalty-Free 32-bit CPU
The D32PRO is a royalty free, silicon proven, high performance soft core of a single-chip 32-bit embedded controller, with Floati…
ISO 7816 Based Smart Card Reader
The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications.
Enhanced Serial Peripheral Interface – Controller IP with single, dual, and quad eSPI Bus support for Intel CPU’s
Smart connectivity for mobile, IoT, and automotive innovation The DI3CS device is an I3C Target that complies with the MIPI® Alli…
64-bit RISC-V CPU with M, Zicsr extensions and External Debug support
The DRV64IMZicsr is a 64-bit RISC-V CPU with M, Zicsr extensions and External Debug support.
The DUTS stands for DCD’s Universal Timers System.
SENT Protocol IP Core for Automotive Communication
The DSENT, a hardware implementation of the Single Edge Nibble Transmission (SENT) protocol controller.
USB 2.0 Human Interface Devices Design Platform
The USB 2.0 HID Design Platform is a , integrated solution, dedicated to a wide range of USB-based Human Interface Devices, like …
USB 2.0 Audio Devices Design Platform
The USB 2.0 Audio Design Platform is a , integrated solution, dedicated to USB-based Audio Devices, like microphones and speakers.
SMBUS & PMBUS Master/Slave controller
The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities.
Our efficient Core performs serial-to-parallel conversion on data received from a IR Receiver Diode.
Introducing DCD’s Ingenious CAN FD IP Core: Empowering Engineers with Unparalleled Flexibility.
The D26C92 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681 with added features and deeper FIFOs.
The D6840 is a programmable timer module, compatible with the 6840 industry standard.