Vendor: Cadence Design Systems, Inc. Category: UALink

UALink Subsystem

224G SerDes PHY and controller for UALink for AI systems

Overview

Efficient Scaling of AI Accelerators for Achieving High Performance and Throughput

UALink, the standard for AI accelerator interconnects, facilitates this scalability by providing low-latency, high-bandwidth communication. As a member of the UALink Consortium, Cadence offers verified UALink IP subsystems, including controllers and silicon-proven PHYs, optimized for robust performance in both short and long-reach applications and delivering industry-leading power, performance, and area (PPA).

Key features

Unmatched Bandwidth, Ultra-Low Latency, and Power Efficiency for AI Accelerators

  • XPU-to-XPU Scale-Up Connectivity — The UALink subsystem IP enables scale-up connectivity for AI systems, supporting the emerging 1.6T and 800G networks
  • Integrated Debugging Features — Includes features like Flit-play for debugging or error injection and Flit-capture for field debugging
  • Multi-Line Rate Support — Supports 100G and 200G data rates
  • FEC Interleave Options — 1-way, 2-way, and 4-way interleaves
  • Optional Features — Packet compression, encryption, and security
  • Standard Features — Atomic support, multiple VCs, bifurcation, UART buffers, DL layer loopback, DL-FLIT play and capture, transmitter pacing, MSG service, programmable RX credit, authentication tags, latency monitoring, and more

Block Diagram

UALink Subsystem block diagram

Benefits

  • Power-Efficient Design: Optimized for UALink
  • Low-Latency: For maximum design performance
  • Proven Solution: Full protocol stack implemented and verified in test chips
  • Long-Reach Capability: Robust 224G 47+dB LR performance with LR/MR/VSR support at reduced power

Specifications

Identity

Part Number
UALink Subsystem
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about UALink IP core

AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP

In this second blog of our ongoing series, we examine how Cadence, in close partnership with TSMC, helps teams accelerate AI silicon design at advanced process nodes. For customers, this translates into reduced design risk, faster convergence to tapeout‑quality results, and greater confidence at the leading edge of AI and HPC design.

UALink Under the Hood: Why Full-Stack Verification Wins

Verifying UALink means following a transaction the way the silicon does: down through four layers, out across one, two, or four SerDes lanes at the configured 100G or 200G serial rate, and back again, with its meaning and its bytes both intact. This blog takes that journey one layer at a time, and along the way examines a detail of the data link flit that is easy to overlook and important to get right.

Securing Scale-Up AI: Cadence’s Complete UALink Solution

As an early contributor to the UALink ecosystem, Cadence delivers a production-ready solution built for real-world AI deployments. By combining high-performance connectivity IP with integrated security, Cadence enables customers to scale AI infrastructure with confidence.

How 224G SerDes Unifies Today’s AI Fabrics

AI system architects no longer face a binary choice between scale-up and scale-out fabrics. Modern AI platforms require both to be executed efficiently, predictably, and within aggressive schedules. The shift lies in how risk is managed across these domains.

Validating UPLI Protocol Across Topologies with Cadence UALink VIP

The UPLI (UALink Protocol Level Interface) is a logical signaling interface that facilitates communication between devices—specifically between originator devices (which initiate transactions) and completer devices (which respond to them). Each transaction comprises a request and a corresponding response, forming a complete communication cycle. Cadence UALink VIP supports various topologies to verify UPLI layer of DUT.

Frequently asked questions about UALink IP cores

What is UALink Subsystem?

UALink Subsystem is a UALink IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this UALink?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UALink IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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