AXI External Peripheral Controller
The AXI External Peripheral Controller (AXI EPC IP Core) supports data transfers between the AXI4 Interface and external synchron…
- System Controller
System peripheral IP cores are essential building blocks in modern SoC and ASIC designs, providing control, management, and support functions for the overall system operation.
This category includes a wide range of peripheral functions such as DMA controllers, interrupt controllers, monitoring and health management blocks, power management controllers, storage-related controllers, system controllers, and timers & watchdogs. These IP cores help coordinate data movement, system supervision, power optimization, fault detection, and overall platform management.
This catalog allows you to explore and compare system peripheral IP cores from leading vendors based on functionality, performance, power consumption, and process node compatibility.
Whether you are designing embedded systems, automotive platforms, or industrial controllers, you can find the right peripheral IP to support your system architecture.
AXI External Peripheral Controller
The AXI External Peripheral Controller (AXI EPC IP Core) supports data transfers between the AXI4 Interface and external synchron…
The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory access between memory and AXI4-Stream-type target…
The Xilinx LogiCORE™ IP AXI Central Direct Memory Access (CDMA) core is a soft Xilinx Intellectual Property (IP) core for use wit…
The AXI BRAM Controller is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK) and Vivado™ IP Integrator…
SATA Host Controller on Spartan 6 LXT FPGA
The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA.
Xilinx provides a Video DMA core for high performance DMA memory access in video processing systems.
The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA S…
SATA Host controller on Virtex 5 FXT
The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
The XPS PS2 Controller is a PLB (Processor Local Bus) slave that is designed to control PS2 devices such as keyboard and mouse.
In a multi processor environment the processors share common resources.
XPS Mailbox features a bi-directional communication channel between two processors.
The XPS HWICAP (Hardware ICAP) IP enables an embedded microprocessor, such as the MicroBlaze™ or PowerPC™ to read and write the F…
Xilinx MicroBlaze Trace Core (XMTC)
This document provides the design specification for the Xilinx MicroBlaze Trace Core (XMTC), which provides instruction and data …
The XPS Timer/Counter is a 32-bit timer module that attaches to the PLB bus.
The XPS Timebase Watchdog Timer Interface is a 32-bit peripheral that connects to the PLB (Processor Local Bus) and provides the …
The XPS Interrupt Controller (XPS INTC) concentrates multiple interrupt inputs from peripheral devices to a single interrupt outp…
XPS External Peripheral Controller
This specification defines the architecture and interface requirements for the External Peripheral Controller (EPC).
The XPS Central DMA Controller provides simple Direct Memory Access (DMA) services to peripherals and memory devices on the PLB.
The XPS BRAM Interface Controller is a Xilinx IP module that incorporates a PLB V4.6 (Processor Local Bus) interface.
ChipScope PRO Virtual Input/Output (VIO)
The LogiCORE™ IP ChipScope™ Pro Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive internal F…