A two-stage secure boot that extends trust from the protected FPGA configuration to the application firmware.
- Boot Firmware Support
System peripheral IP cores are essential building blocks in modern SoC and ASIC designs, providing control, management, and support functions for the overall system operation.
This category includes a wide range of peripheral functions such as DMA controllers, interrupt controllers, monitoring and health management blocks, power management controllers, storage-related controllers, system controllers, and timers & watchdogs. These IP cores help coordinate data movement, system supervision, power optimization, fault detection, and overall platform management.
This catalog allows you to explore and compare system peripheral IP cores from leading vendors based on functionality, performance, power consumption, and process node compatibility.
Whether you are designing embedded systems, automotive platforms, or industrial controllers, you can find the right peripheral IP to support your system architecture.
A two-stage secure boot that extends trust from the protected FPGA configuration to the application firmware.
Input/Output Memory Management Unit
SMMUv3 · Two-stage translation · DMA protection
SmartDV’s UFS (Universal Flash Storage) 5.x Device IP is a next-generation storage interface solution designed for flash memory c…
DTI_DMA control the DMA transfers data between different points in the memory space without intervention of the CPU.
The Mailbox IP is the communication channel between the internal system and the host processors.
The Basic Timer consists of a 32-bit auto-reload counter driven by a programmable pre-scaler.
The Adv_Timer (-control Timers) consist of a 32-bit auto-reload counter driven by a programmable prescaler.
The RTC (Real Time Clock) provides an automatic wake-up to manage all low-power modes.
The WWDG (WindowWatchdog) is used to detect the occurrence of a software fault, usually generated by external interference or by …
The IWDG (Independent Watchdog) is suited to applications which require the watchdog to run as a totally independent process outs…
Direct Memory Access Controller
The uDMA (Micro Direct Memory Access) controller serves as a hardware approach for direct data transfers between peripherals/memo…
SD Card Input/Output Protocol Controller
SDIO protocol is evolved and upgraded from the SD card protocol.
Compliant to NVM Express 1.4 specification
The NVMe Verification IP (VIP) and Post-Silicon Validation Suite are based on the latest protocol standards (NVMe 1.2) from www.n…
Automated Hierarchical Test for Analog/Mixed Signal IPs The SLM SHS IP is an automated hierarchical test solution for efficiently…
SD 4.1 Host Controller Software Stack
This is a production-ready stack for Arasan’s eMMC Host Controller IP that is used to connect to SD, SDIO, or eMMC devices.
The NVMe Gen 5 Controller Verification IP ensures that storage systems operate efficiently at 32 GT/s data transfer rates.
UFS Controller - Verifies compliance and performance of UFS interfaces in SoCs
The UFS Controller Verification IP (VIP) ensures proper operation and compliance of UFS interfaces in SoC designs.
The SD Card Controller Verification IP (VIP) is a tool designed to ensure the proper functionality and performance of SD card mem…
The Scatter-Gather DMA Engine Verification IP (VIP) is designed to validate the functionality and performance of scatter-gather D…