Programmable Peripheral Interface
The D8255 is a programmable I/O device, designed to be used with all Intel CPUs.
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System peripheral IP cores are essential building blocks in modern SoC and ASIC designs, providing control, management, and support functions for the overall system operation.
This category includes a wide range of peripheral functions such as DMA controllers, interrupt controllers, monitoring and health management blocks, power management controllers, storage-related controllers, system controllers, and timers & watchdogs. These IP cores help coordinate data movement, system supervision, power optimization, fault detection, and overall platform management.
This catalog allows you to explore and compare system peripheral IP cores from leading vendors based on functionality, performance, power consumption, and process node compatibility.
Whether you are designing embedded systems, automotive platforms, or industrial controllers, you can find the right peripheral IP to support your system architecture.
Programmable Peripheral Interface
The D8255 is a programmable I/O device, designed to be used with all Intel CPUs.
The D8254 is a programmable interval timer/counter, binary compatible with the 82C54 industry standard.
UFS Hardware Validation Platform (HVP)
Universal Flash Storage (UFS) is a simple, high performance, mass storage device with a serial line interface.
The SD Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Interface of an AS…
The SD Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Interface of an AS…
The Tessent Embedded Software Development Kit (ESDK) is a set of software libraries designed to be compiled and run on an embedde…
The Tessent Embedded Analytics solution can be used to produce health and operational metrics throughout the lifecycle of an SoC.
Tessent Automotive IC debug and optimization
Vehicles are becoming complex systems approaching billions of lines of code.
Tessent AI IC debug and optimization
The multicore architectures of SoCs for machine learning (ML) and artificial intelligence (AI) applications provide unique challe…
Tessent Static Instrumentation
The Tessent Embedded Static Instrumentation module provides a nonintrusive mechanism for code instrumentation.
Tessent SoC debug and optimization
Tessent Embedded Analytics accelerates debug, validation, and optimization of complex multi-core SoCs.
SD/SDIO Combo Device IP core is an SD memory controller and an SDIO controller with an AHB interface.
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The CC-WDT-APB is a synthesisable Verilog model of a watchdog timer controller.
Configurable System Tick Counter
The CC-SYSTICK-APB is a synthesisable Verilog model of a system tick timer counter controller.
The CC-TIMER-APB is a synthesisable Verilog model timer counter controller.