Vendor: eInfochips Category: NVMe Controller

NVMe Verification IP

The NVMe Verification IP (VIP) and Post-Silicon Validation Suite are based on the latest protocol standards (NVMe 1.2) from www.n…

Verification IP View all specifications

Overview

The NVMe Verification IP (VIP) and Post-Silicon Validation Suite are based on the latest protocol standards (NVMe 1.2) from www.nvme.org. These are available from elnfochips for licensing with support and related services.

NVMe Services

elnfochips offers industry leading expertise on NVMe for flash based SSD storage products. This includes design, verification and system validation for ASIC and FPGA. Customers can accel erate product design schedule for RnD teams while reducing product and performance risks with proven solutions and services.

NVMe Validation Suite

elnfochips NVMe Post-Silicon Validation Suite enables test scenarios that are defined by UNH-IOL (University of New Hampshire - Interoperability Lab) for performance and interoperability. It also covers other test scenarios for greater confidence on the product design and performance. It supports Windows and Linux OS.

NVMe Verification IP

The NVMe VIP is interoperable with other third party VIPs like PCle or SATA for a modular and comprehensive verification environment. This VIP is fully compliant to UVM, OVM, VMM and SystemVerilog.

Key features

NVMe VIP:

  • NVMe 1.2 Compliance
  • User configurable Admin/IO queue size and configuration Admin commands for IO queues and NVM read/write, reset, abort, identify, get and set features
  • Supports PRP and PRP List
  • All interrupt reporting: pin-based, single message MSI, multiple messages MSI, MSI-X
  • Exhaustive checkers
  • Exhaustive functional coverage
  • Hook-ups for score boarding and additional processing
  • Bandwidth calculator per direction per component
  • Works with other PCle VIP and custom BFM/IF

NVMe Validation Test Suite

  • System level test scenarios not covered by UNH-IOL
  • Create I/O Submission queue without creating associated I/O
  • Completion queue
  • Same Command ID for two commands in a Submission queue
  • Invalid SGL Segment location
  • Common OS abstraction layer test suite for Linux and Windows OS
  • Enhanced tNVMe as per test scenarios requirements
  • QEMU based NVMe software mode

Block Diagram

Specifications

Identity

Part Number
NVMe Verification IP
Vendor
eInfochips
Type
Verification IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about NVMe Controller IP core

Timing Optimization Technique Using Useful Skew in 5nm Technology Node

The relentless march towards shrinking technology nodes has ushered in a new era of intricate semiconductor designs characterized by a proliferation of transistors. This intensifying complexity brings with it heightened criticality in various aspects of chip design and manufacturing. As each day dawns, innovative techniques and methodologies emerge to tackle these burgeoning challenges and fortify the compatibility of cutting-edge electronic devices.

BCD Technology: A Unified Approach to Analog, Digital, and Power Design

Since its inception, BCD technology has leveraged the integration of two primary technologies—polysilicon gate CMOS and DMOS power architecture—on the same chip. Its compatibility with bipolar components has enabled the creation of SoCs (System-on-Chip) that combine digital and analog control with efficient power management sections.

Frequently asked questions about NVMe Controller IP cores

What is NVMe Verification IP?

NVMe Verification IP is a NVMe Controller IP core from eInfochips listed on Semi IP Hub.

How should engineers evaluate this NVMe Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this NVMe Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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