Multi-world Hardware Isolation for System Security

SiFive Insight is a trace and debug portfolio that accelerates HW/ SW validation for standalone SiFive RISC-V designs or mixed vendor environments. Included with all SiFive Core IP licenses, the base framework provides essential run control, core interrogation, and hardware triggers. For deeper visibility, customers can easily add a Nexus 5001 compliant hardware trace encoder to any SiFive Core IP, capturing precise execution histories without intrusive software logging.

Challenge

How to efficiently develop, debug, and validate increasingly complex System-on-Chip (SoC) designs in multi-core and mixed ISA solutions while providing deep visibility into HW/SW behavior without altering the execution timing.

Solution

SiFive Insight provides a comprehensive hardware driven portfolio that combines standard run control debug with Nexus 5001 compliant hardware encoder capabilities. Configured via SiFive Core Designer, the solution allows developers to monitor and record the real-time execution of code and data movements inside the chip without having to halt the processor or the overhead software instrumentation.

Impact

System architects and software engineers deliver solutions faster with more efficient HW/SW validation timelines. By minimizing workflow disruption and integrating cleanly with existing third-party environments, engineering teams can ultimately accelerate silicon bring-up, HW/SW tuning, SoC integration, and overall time-to-market.

ARCHITECTURAL HIGHLIGHTS

Standard Debug for Run Control and Security

The Debug Module (DM) enables CPU run-control (halt, resume, step) via standard JTAG or cJTAG interfaces. It features up to 16 hardware breakpoints and optional System Bus Access (SBA), bypassing memory protection for zero impact, real-time memory reads and writes on any core for zero performance impact debugging. An Authentication Module enforces password, public-key, and optional WorldGuard security integration before granting access.

Advanced Trace Subsystem (Nexus 5001 Compliant)

A Nexus 5001-compliant Trace Encoder for non-intrusive execution and event tracking with message timestamping. It supports Branch Token Messages (BTM) for smaller cores or History Trace Messages (HTM) for better message compression on high-performance multi-core designs. New technology includes Event Trace that records a trace message only when specific system events occur and Profiling Performance Counters (PPCs) that track specific metrics between two distinct events, with no performance impact.

Native Arm® CoreSight™ Compatibility

SiFive Insight natively integrates with the ARM CoreSight architecture using a bridge that translates Nexus trace data into the Advanced Trace Bus (ATB) protocol, allowing developers to debug ARM and RISC-V SoCs using existing ARM tools. The solution utilizes an AMBA Advanced Peripheral Bus (APB) interface and an APB Debug Transport Module (DTM) that allows an Arm Debug Access Port (DAP) to directly control the SiFive cores.

• External Debug Ports: Debug over JTAG, 2-wire cJTAG, or ARM-compatible AMBA APB interfaces.
• Advanced Core Triggers: Up to 16 hardware breakpoints and 16 external cross triggers per core to halt or resume based on events.
• System Bus Access (SBA): Optional, non-intrusive memory access block for real-time variable read/write without affecting CPU cores.
• Nexus Trace Encoding: Supports open IEEE-ISTO 5001 standard address/opcode compression with selectable Branch Taken Messages (BTM) or History Trace Messages (HTM).
• Zero-Overhead Event Trace: Tracks call/return sequences, exception boundaries, context changes, and interrupts with timestamps with no software instrumentation.
• Profiling Performance Counters: Tracks hardware counters and provides metrics between definable events.
• Multilayered Debug Access Control: Enforces strict TAP security through fused permanent disable pins, 32-bit password barriers, or public-key cryptographic authentication.

• Heterogeneous SoC Debugging
• Domain Specific Accelerators
• Complex SoCs
• Cost Effective Development Kits