Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: DAC

SMIC 0.18um 24Bit Sigma-Delta DAC

The SMIC18_DAC_01B specifies the design of a high-performance 24-bit stereo Audio DAC for portable digital audio systems.

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24 Bit SMIC 180nm G View all specifications

Overview

The SMIC18_DAC_01B specifies the design of a high-performance 24-bit stereo Audio DAC for portable digital audio systems. The DAC within the specification uses sigma-delta technique. Analog output signals including stereo output of the SMIC18_DAC_01B are single-ended. The internal stereo headphone amplifier is capable of driving 16Ω load.

Key features

  • Process: SMIC standard 0.18um /3.3V logic 1P6M
  • Single-Ended DAC --THDN:-90dB@-6dB Fs Input --Dynamic Range, SNR: 100dB
  • Audio Serial Interface --32bit word length --I2S mode
  • 2-wire Serial Control Interface
  • Master Clock is 256fs
  • Sampling Rates --8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 96kHz
  • Power Supply --1.8V Core Digital Supply, typ. (1.62~1.98V) --3.3V Pad and Analog Supply, typ. (2.6-3.6V)
  • Highly efficient Linear Headphone Amplifier
  • Internal PLL as the Audio DAC Master Clock Generator
  • Output Mux to bypass FM signal to output
  • Out-PGA: 0dB~-60dB, -2dB step with analog mute
  • Supports Multiple OSC Frequency: 8.192M, 12M, 12.288M, 13M, 13.5M, 19.2M, 21.25M, 24M, 26M, 27M, 38.85MHz
  • Power Dissipation: 3mA @ Ultra Low Power Mode
  • Operating Junction Temperature: -40 ~ 125C

Silicon Options

Foundry Node Process Maturity
SMIC 180nm G —

Specifications

Identity

Part Number
SMIC18_DAC_01B
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Analog

Resolution bits
24 Bit

Provider

Contact VeriSilicon Microelectronics (Shanghai) Co., Ltd.

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is SMIC 0.18um 24Bit Sigma-Delta DAC?

SMIC 0.18um 24Bit Sigma-Delta DAC is a DAC IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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