Overview
The Verification IP (VIP) for eUSB is a complete VIP solution for the Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Revision 1.1. It provides a mature and comprehensive verification IP (VIP) for the eUSB protocol. Incorporating the latest protocol updates, the eUSB2 VIP is not only just a complete bus functional model (BFM) for the DUT operating in eUSB Native Mode but it also provides integrated automatic protocol checks and coverage model.
This VIP for eUSB provides support for any eUSB device in native mode: Host(eDSPn) or Device(eUSPn), in Repeater Mode: Host(eDSPr) or Device(eUSPr), Host Repeater, Peripheral Repeater and Hybrid Repeater. . It supports all eUSB operational speeds: Low, Full, or High. It provides multiple signaling eUSB interfaces: single-ended signaling for low-/full-speed mode and low-voltage differential signaling for high-speed mode to test and monitor all possible configurations of USB devices. The eUSB VIP is designed in such a way that it is easy for you to integrate in testbenches for IP, System-on-chip (SOC) and system level. The eUSB VIP helps you to reduce time to test by accelerate verification closure and ensure end product quality.
The VIP for USB runs on all major simulators and supports all main verification languages such as Verilog, System Verilog and e alongside with industry-standard methodologies for Testbench writing such as Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specifications: eUSB2 v1.1, USB2.
The following are the key features from the specifications that are implemented in the VIP:
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Feature Name
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Description
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Supported DUT Types
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- All eUSB DUT types, such as in native mode: Host(eDSPn) or Device(eUSPn), in Repeater Mode: Host(eDSPr) or Device(eUSPr), Host Repeater, Peripheral Repeater, and Hybrid Repeater
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Transaction Types
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- All types of transfers: bulk, control, interrupt, and isochronous transactions
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Backward Compatible
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- Backward compatibility with USB 1.1 specifications
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Enumeration
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- Provides a complete USB protocol hierarchy enumeration process for host and device models
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Operational Speed
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- Operates at high, full, or low speed
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Reset Signaling
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- Supports low/full-speed reset and high-speed chirp handshake
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Suspend/Resume
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- Supports suspend, resume, remote wake-up, and low-power management (LPM)
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Transaction and Packet Checks
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- Checks for all transaction and packet rules including inter-packet gap and propagation delays
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Protocol Features in Repeater mode
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- Support for glitch handling
- Support for variable SYNC bits handling
- Support for first distorted SYNC bit handling
- Support for dribble handling
- Support for SE1 skew handling
- Support for port reset in all states
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Translator
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- Digital translator available for sending eUSB-compliant traffic
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Register interface
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- Support to change the severity (Error, Warning, Info) of the protocol assertions
- Support to initiate various commands such as reset, suspend/resume/remote wake-up, disconnect/connect, and so on
- Support to control the functionality such as end-point buffers, chirp sequence, and clock frequency
- Support to store information of the VIP model such as, device states, device address, end-point information, and other information that is easily accessible by the testbench
- Support to insert error injections at the eUSB Phy
- Support to initiate go to Port Reset from any state, issue silent and soft disconnect by device (eUSPn)
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Predefined Error Injections
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- Device drives Port Reset during POR
- Host drive ED+ as 1 instead of driving SE1 in Port Reset
- Device corrupts the ACK in Port Configuration
- Device drives invalid Connect Signal depending on the speed of operation
- Device drives invalid ping
- Host does not send an EOP
- Host drives J signal instead of K during the resume operation
- Host does not drive Resume signal after Remote wakeup from device
- Host sends corrupted EOP to the device
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Learn more about USB IP core
USB4 systems rely on retimers to enable reliable high-speed communication across complex topologies where maintaining signal integrity over extended channels is a significant challenge. Retimers act as intermediate elements that restore signal quality at each hop by performing clock and data recovery (CDR) and retransmitting a clean, regenerated signal.
The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.
When a new interface technology emerges, specs and simulations are only part of the story. What customers and partners truly need is confidence that the ecosystem can work, in practice, across chips, controllers, PHYs, platforms, and devices.
Earlier this year, Cadence achieved a major milestone with the tapeout of the first 3nm eUSB2V2 PHY test chip, now fully validated and completing silicon characterization. Building on this success, Cadence has developed a complete end-to-end eUSB2V2 solution, including both host and device controller IP.
Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for AI-based designs, including Ultra Accelerator Link (UALink), Ultra Ethernet (UEC), LPDDR6, UCIe 3.0, AMBA CHI-H, Embedded USB v2 (eUSB2), and UniPro 3.0.
Morgan State University (MSU) recently received an Apple Innovation Grant, designed to support engineering schools as they develop their silicon and hardware technologies. The New Silicon Initiative (NSI) is designed to inspire and prepare students for careers in hardware engineering, computer architecture, and silicon chip design.
