AI Accelerator IP Listing

The UALink Controller delivers ultra-low latency and high-bandwidth interconnects that enable seamless scale-up connectivity between AI accelerators

• UALink

RapidFlex eFPGA IP provides a reconfigurable, upgradeable, and iterative logic computing layer for SoCs, MCUs, AI accelerators, i…

• eFPGA

Our Standard Cell Libraries are designed to meet the rigorous demands of modern semiconductor applications, including automotive,…

• Standard Cell Libraries

The GDDR7 controller IP core is designed for use in applications requiring high memory throughput including artificial intelligen…

• Controller

The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, a…

• CXL
• Available on request
• Available

Optimized for 3D Wafer-on-Wafer (WoW) integration, the controller supports ultra-wide interface.

• Controller

SLC / L3 · 4 MB–32 MB+ · CHI HN-F

• Coherency

Expands effective bandwidth across links and memory interfaces with deterministic, data-independent latency, fully pipelined to sustain line rate

• Data Compression

SmartDV’s UCIe 3.x Controller IP is a next-generation Universal Chiplet Interconnect Express solution engineered for the most dem…

• Controller

Rambus offers the industry’s fastest HBM4E Controller IP core designed to support customers with deploying a new generation of HB…

• Controller

The 56G/64G PAM4 SERDES hard macro IP delivers a high-performance, low-power solution for high-speed serial interfaces.

• Single-Protocol PHY

The UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets, fully compliant with the Universal …

• UCIe

The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.

• Multi-Protocol PHY

The PCI Express® (PCIe®) Controller IP is a configurable, performance-optimized core designed for ASIC and FPGA integration.

• PCI Express

The GDDR5 Memory Controller Verification IP (VIP) is a robust solution designed to verify the compliance and performance of GDDR5…

• Controller

Rambus is offering the industry’s first HBM4 Controller IP core designed to support customers with deploying a new generation of …

• Controller

The UCIe Controller IP is a configurable and customizable UCIe 1.1 compliant die-to-die controller.

• UCIe
• Available on request
• UCIe 1.1

UCIe D2D · CHI Rev E.b · Mesh & Ring · iNoCulator-generated RTL

• Network-On-Chip

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…

• CXL
• FPGA proven
• Immediate
• CXL V2.0

Traditional processors no longer strike the right balance between high performance, energy consumption, and cost.

• RISC-V