AP Memory VHM Controller

Mobiveil’s Controller for AP Memory VHM™ (Very High Bandwidth Memory) Technology is a high-Performance, ultra-low-latency IP solution engineered to harness the full potential. Optimized for 3D Wafer-on-Wafer (WoW) integration, the controller supports ultra-wide interface that delivers very high bandwidth directly to the processing unit. AP Memory VHM™ devices can support up to several TB/s when fully utilized. One such example is a small footprint memory solution that can provide up to 2TB/s with Mobiveil’s Controller instantiated multiple times for use in multi-channel architecture of VHM™. The solution is scalable for higher bandwidth beyond 2 TB/s as well. The VHM™ Controller is part of Mobiveil’s memory controller family of IP solutions. AP Memory VHM™ acts as a high-capacity scalable DRAM solutions. It provides 4GB multi-bank architecture that ensures superior timing and throughput. The controller features a highly configurable, layered architecture that is fully compliant with AMBA4 AXI4 and custom DFI 4.0 specifications, offering a low-risk path for integration into Edge AI accelerators, HPC processors, and networking engines. The controller’s configurable and layered architecture is independent of application logic, implementation tools, and most importantly, the target technology. Its flexible AXI system interface makes it easy to integrate into a wide range of applications. The VHM controller leverages Mobiveil’s years of experience in AP Memory ApSRAM™, DDR4, NVMe, and Rapid IO technologies, creating system-validated IP solutions with RTL, synthesis, simulation, board, and software elements to offer the lowest risk in terms of compliance and interoperability.

• Compatible with ‘AP Memory VHMTM WoW 3D Stacked DRAM.
• Protocol Compliance: Compliant with required AXI4 features and AP Memory specifications.
• Advanced Interface: Supports a custom DFI 4.0 interface and memory data widths of 256 bits and AXI width conversion, if required.
• Multi-Bank Efficiency: Utilizes an 8-bank architecture to maximize bus efficiency through bank-level parallelism.
• Intelligent Scheduling: Maximizes throughput via look-ahead command processing and intelligent request scheduling.
• Flexible Configuration: Features configurable request queue depths and data FIFO sizes.
• Power Management: Supports self-refresh, auto-refresh, and deep power-down modes,
• Data Reliability: Provides Read-Modify-Write (RMW) support for unaligned, narrow AXI transfers and when the total transfer size is not aligned to 64-byte memory word boundary

Other:

• Many key features are user configurable via CSR
• AXI Sync vs Async option

• Highly modular and configurable design
• Layered architecture
• Fully synchronous design
• Supports both sync and async reset
• Clearly demarked clock domains
• Software control for key feature

• Verilog RTL Code
• UVM-based test bench and behavioral models
• SystemC AT Model
• Test cases, Protocol checkers and performance monitors
• Synthesis scripts

Documentation

• Design Guide
• Verification Guide
• Synthesis Guide