CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…
- CXL
- Immediate
- CXL V3.0/V2.0
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…
The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
CXL Controller With HPC Features (Spec Version 3.0 and Above)
Supports CXL 4.0 spec at 128GT/s and full backwards compatibility with CXL 3.x, 2.0, and 1.x
VIP for Compute Express Link (CXL)
Synopsys Verification IP (VIP) for CXL provides verification of design implementations based on CXL specifications which can be u…
Most advanced PHY and controller IP for HPC, AI/ML, data communications, networking, and storage systems
Adds security Interfaces, features to CXL 3.0 Premium controllers
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
Most advanced PHY and controller IP for HPC, AI/ML, data communications, networking, and storage systems
CXL Controller (Spec Version 2.0 and Below)
The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, a…
CXL 3.0 Integrity and Data Encryption Security Module
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…
32G NRZ Multi-Protocol PHY
CXL 2.0 Integrity and Data Encryption Security Module
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…
CXL Host Device Dual mode controllers
Primesoc's CXL IP supports dual mode of Host and device , integrated with PCIE Gen5 and well tested.
The ICE-IP-63 (EIP-63) is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well …
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
Universal Chiplet Interconnect Express (UCIe™) PHY and Controller
High-bandwidth, low-power and low-latency standardized die-to-die interconnect
UCIe Controller add-on CXL2 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller add-on CXL3 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…