Synopsys Verification IP (VIP) for CXL provides verification of design implementations based on CXL specifications which can be u…
Synopsys Verification IP (VIP) for CXL provides verification of design implementations based on CXL specifications which can be used in SoCs and system level designs to accelerate verification closure. Synopsys VIP provides support for various CXL protocol including CXL.io, CXL.cache, CXL.mem, enabling verification for all device types.
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Category |
Feature |
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Specification Version |
CXL 1.1, CXL 2.0, CXL 3.0, CXL IDE, CXL CXS.b, CXL LPIF 1.0, PCIe Base- 5.0/6.0, PIPE- 5.2/6.1 |
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DUT Configuration |
HOST, Device |
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Protocol Support |
CXL.io, CXL.cache, CXL.mem, PCIe Only |
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Interface |
Serial PIPE, SERDES, CXL over CXS ULL, CXL Over CXS LLL |
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Device Type |
Type 1 – CXL.io + CXL.cache Type 2 – CXL.io + CXL.mem + CXL.cache Type 3 – CXL.io + CXL.mem |
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Topology |
PCIe TLMs at TL/DL, CXL.io/mem/cache TLM, CXL Flit TLM - CXL Req/ Data/Resp TLM, Logical PHY Interface (LPIF) v 1.1, PCIe LPC, PIPE SerDes Architecture, Serial |
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Link Speeds |
64 GT/s, 32 GT/s and degraded mode of 16 GT/s and 8 GT/s |
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Link Width |
Native Width (x16, x8, and x4) and degraded width (x2, x1) |
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Security |
IDE, DOE |
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Flit Support |
256B standard, 256B Lopt, 68B, and all other flit types supported for each layer |
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IO/Cache/Mem |
All types of IO, Cache and Mem Flows, Back-Invalidation Host, Device Bias mode, Retry flow, Viral and Poison, QoS telemetry |
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ARB/MUX |
All Power Saving states, Weighted Round Robin, Arbitration Bypass mode |
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Registers |
Configuration Space Registers, Memory Mapped Registers |
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Flex Bus |
Alternate Protocol Negotiation, Framing Error Handling, Synch Header Bypass |
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Initialization and Enumeration |
CXL 1.1, 2.0 and 3.0 enumeration, Link Layer Initialization, Bypass Enumeration |
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Analysis |
Protocol Analyzer, Scoreboard, Protocol Checks at each level, Functional Coverage |
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Simulator |
Support all Major Simulators |
|
Methodology |
Native SystemVerilog/UVM |
Note: some files may require an NDA depending on provider policy.
VIP for Compute Express Link (CXL) is a CXL IP core from Synopsys, Inc. listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CXL IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.